Metrology for Advanced Packaging
With new chip packaging techniques, including 2.5D, 3D-IC, fan-out wafer-level packaging and system-in-package, the need for flexibility in wafer metrology and handling has exploded.
Mastering manufacturing complexity in advanced packaging technologies. FormFactor FRT Metrology tools measure and handle numerous wafer types up to 12 inches for both front and back end: bare, structured, coated, bonded, highly warped, thinned, TAIKO and fan-out wafers. Capabilities extend to wafers with Micro-Electronic-Mechanical Systems (MEMS) components, and wafer stacks at various 3D packaging process steps, as well as glass, lens, and non-SEMI-standard wafers, panels and film frames.
The included dual arm robot handling unit can be configured for 300 mm, 200 mm, and 150 mm wafers and panels, either exclusively, or as a bridge tool to allow the handling of two sample sizes within one metrology tool.
Going beyond expectations.
Post Chemical Mechanical Polishing (CMP) Wafer Inspection
Detrimental surface irregularities after CMP with increasing number of layers and process steps lead to electrical chip defects and lower wafer yield. Measuring those irregularities on die areas or even on entire wafers enables the monitoring of the post-CMP process with sub-nanometer resolution.
The FRT White Light Interferometer Sensor evaluates the flatness of die areas with a full shot sizing ~25 mm x 35 mm and larger in ~30 min, with Z-resolution of 0.1 nm. Thanks to its image stitching capability, our automation software can create a high-resolution image of the full wafer.
Even Smaller Structures through Redistribution Layers (RDL)
An RDL generally aims to make packages even smaller by rerouting connections to different locations on a chip. Using RDLs, metal pads on the wafer lead to redistributed bumps – with a very precise and well-controlled manufacturing process. Important parameters are thickness, width and roughness.
For the evaluation of RDL height and width we use White Light Interferometry (WLI) with optimized setup for high resolution and excellent repeatability. Bump heights, widths, pitch and coplanarity are monitored according to JESD22-B108 standards.
With White Light Interferometry we successfully analyze the width and spacing of RDLs to within single-digit microns.
Automated Bump Inspection of Die
On each die, different components are connected with individual bumps or with bump arrays. The bump dimensions and coplanarity provide insights into the electrical contact and functionality of the device.
Bump and μ-bump measurement are typical measuring tasks in high volume manufacturing process control. Our metrology tools measure the bump heights, widths, pitch and coplanarity according to JESD22-B108.
With our software it is possible to process a fully automated bump inspection from topography data. In this case, coplanarity, bump height and bump diameter are determined automatically.
Vias and Trench Measurement with Specialized Optical Sensors
Shortening paths by using silicon vias vertically through the chip (TSVs) improves a chip’s performance regarding bandwidth and power consumption. For the process control of via depth, top and bottom critical dimension we use white light interferometry. High aspect ratios (up to a 1:20 ratio) of the TSV’s diameter and depth make analyses only possible for specialized optical sensors.
The top critical dimension is measured by the FRT Confocal Microscope DT. For the TSV depth, we use the FRT IRT sensor.
Fast and Reliable Critical Dimension and Overlay Process Control on Photo Wafers with High Lateral and Vertical Resolution
Critical dimension (CD) refers to one or more qualities of a test structure which allow systematic statements to be made about the quality of the manufacture of a process step. The control of the CD value and the overlay shift are among the most important sub steps in the manufacture of microelectronic products.
Typical measurement tasks are process control of outer CD, inner CD and overlay using high-resolution, as well as the quantitative output and graphical visualization of overlay misalignment.
