2016

Advanced Testing Technology for Emerging Automotive Applications | Stillman, Leong, Bhardwaj

Vertical MEMS Probe Technology For Advanced Packaging | Leong

 

2015

Review of New, Flexible MEMS Technology to Reduce Cost of Test for Multi-site Wire Bond Applications | Stillman, Eldridge

High performance HBM Known Good Stack Testing | Loranger, Oonk

Determining Probe’s Maximum Allowable Current | Cassier, Folwarski, Kister, Leong
Winner of “Most Inspirational Presentation”

Minimizing Parametric Probe Card Stray Capacitance | Soler, Levy

 

2014

Reliable Testing of Cu Pillar Technology For Smart Devices  | Bezuk, Cassier, Leong, Miller, Slessor, Syed, Zhao

Cost Effective 1,000V High Voltage Parametric Test Technique | Andoh, Ishibiki, Kawamata, Funatoko

Advance Low Force Probe cards Used on Solder Flip Chip Devices | Stillman, Hughes

Key Considerations to Probe Cu Pillars in High Volume Production | Wittig, Leong, Nguyen, Masi, Kister, Slessor
Winner of “Best Overall Presentation”

Can testers and probe cards keep up with speed requirements for image sensors? | Levy, Kawamata, Hamajima

International Technology Roadmap for Semiconductors | Armstrong, Feldman, Loranger

 

2013

Use of Resource Sharing Techniques to Increase Parallel Test and Test Coverage in Wafer Test | Huebner

Methods of Analyzing/Predicting Scrub Margin for Pads and Bump Applications | Watson

Probing Study of Fine-pitch Cu Pillars | Leong, Wittig, Nguyen, Hulic, Slessor

Trends, Challenges, and Solutions in Advanced SoC Wafer Probe | Slessor, Kister, Eldridge, Nguyen, Leong

When Brick Wall is Not the Best, PART II (A Touch Down Optimization Study) | Wegleitner, Berry

Beyond ISMI: Electric Current Capacity of Vertical Probes Under Pulsed and Transient Signals | Hughes

 

2012

IEEE Semiconductor Wafer Test Workshop, 28nm Mobile SoC Copper Pillar Probing Study | Horas, Leong, Hulic

Is parametric testing about to enter a period of growth and innovation? | Levy

28nm Mobile SoC Copper Pillar Probing Study | Horas, Leong, Hulic

Crossover in TD efficiency – When Brick Wall is Not the Best | Breinlinger

Actual vs. Programmed Over Travel for Advanced Probe Cards | Berry, Breinlinger, Rincon

 

2011

A HOT Topic: Current Carrying Capacity, Tip Melting and Arcing | Huebner

IEEE Semiconductor Wafer Test Workshop, A Flexible Vertical MEMs Probe Card Technology for Pre-Bump and eWLP Applications | Slessor & Marshall

IEEE Semiconductor Wafer Test Workshop, Evaluation of New Probe Technology on SnAg and Copper Bumps | Wittig, Leong, Hulic

IEEE Semiconductor Wafer Test Workshop, Key Design Parameters to Maximize Probe Current Carrying Capability | Kister
Winner of “Best Paper-Tutorial in Nature”

Wafer Probes: 8 Parameters for Current-carrying Capability in Semiconductor Test | Kister

 

2010

Benefits of Flip Chip Wafer Sort using MEMs Multi Site Capability | Tick, Pierra

Addressing the Operating Challenges of Full Wafer Contactors | Breinlinger

Expanding Test Coverage at Sort to Reduce Overall Product Costs | Levy

High Speed Control Bus for Advanced TRE™ | Huebner
Winner – Best Presentation, Tutorial in Nature

Semicon West TechSITE North, Meeting the Economic and Technical Challenges of Wafer Test Slessor

 

2009

Highest Parallel Test for DRAM Enabled through Advanced TRE (Tester Resource Enhancement) | Huebner

Improving Scrub Performance and Reducing Soak Time with a New Mechanism to Stabilize Probe Card Temperature | Harker, Lin, Pearce

MicroProbe Vx-RF Probe Card Technology | Slessor, Kister, Degan, Nagler, Nouri

IEEE Semiconductor Wafer Test Workshop, MicroProbe Vx-RF Probe Card Technology | Nagler, Degen, Nouri, Kister & Slessor

 

2008

MicroProbe Vx-MP Probe Card Technology | Kister, Hopkins

40k Probes on 300mm Probe Card – another step towards 1 touchdown DRAM SORT | Huebner

IEEE Semiconductor Wafer Test Workshop, MicroProbe Vx-MP Probe Card Technology | Kister & Hopkins

 

2007

Electrical Contact Resistance – The Key Parameter in Probe Card Performance | Kister, Hopkins
Winner – Best Data Presentation

Wafer Probing Scrub Analysis to Optimize KGD Applications | Wang, Martens, Wijeyesekera, Matsubayashi, Napier, Leong

Key Methods in Reducing Pad Crack Risk at Probing Low-k Wafers | Romreill, Leong

Probes A New Dimension in Probe Count | Huebner, Hatsumori, Pritzkau, Kawamata, Matsuo

IEEE Semiconductor Wafer Test Workshop, Electrical Contact Resistance – The key Parameters in Probe Card Performance | Kister & Hopkins

 

2006

One Touch 300mm Wafer Probing | Wijeyesekera, Shinde

 

2005

DDR2 DRAM High-Frequency Test at Probe (HFTAP) | Ozawa, Funatoko

 

2004

Cost-Effective Fully Tested Die with High Frequency and High Throughput Wafer Test Solution | Ozawa, Minamihashimoto, Sagamihara

Optimization of MicroSpring® Contact Design Parameters for Low Pressure Probing | Martens, Levy

Click the links at left to view our publications.