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2021

Too Hot to Test for Leading-edge SoC and Heterogenous Integrated IC Stack | Leong
Presented at TestVision 2021

Leading-edge AI/Graphic/mobile processors, DRAM devices, and heterogeneous integrated IC stacks are all facing the same set of thermal management challenges -- the DUT is too hot to test. Even at room temperature wafer chuck setting, a mobile SoC device junction temperature can get well above 100 to 150C. For DRAM full-wafer testing, 1-2K watts of power could be applied during 1-TD testing, posting challenges for test cell thermal management. This results in inaccurate test results or frequently burned probes which cause test cell downtime.  As the heterogeneous integration becomes more popular, the thermal challenges to test the base-die with multi-chips stacked on top further exuberate as the thermal loading per silicon area can increase by order of magnitude. You can’t improve what you can’t measure. FormFactor latest low-thermal-resistance (LTR) wafer chuck technology applies multiple temperature sensors to accurately detect DUT temperature and adjust heat dissipation to achieve the desired test temperature. LTR has shown promising results in production test to address the too hot to test challenge.

Next Generation KGD Memory Test Achieved Wafer Level Speed Beyond 3GHz | Lee
Presented at TestVision 2021

Recent industry wide adoption of heterogeneous integrated system enabled by 2.5D and 3D advanced packaging technology is driving up the demand for known-good-die (KGD) and known-good-stacked-die (KGSD). Coupled with the advancement on DRAM and High Bandwidth Memory (HBM) native speed capability, the latest memory is running beyond 2GHz (4Gbps) which is pushing the limit on existing ATE testers. Recent joint effort between SK Hynix, FormFactor, and Advantest successfully demonstrated that beyond 3GHz is achievable. This session discusses the design challenges overcame in this collaboration from a system level signal integrity and power delivery perspective.

Digital Revolution: PAM4 Wafer Test | Raschko
Presented at TestVision 2021

As data rates continue to increase, the difficulty of increasing clock rates for improved bitstreams becomes more challenging with ever-increasing loss. As of today, Non-Return-to-Zero (NRZ) is the standard for digital encoding, but this begins to run into problems with loss and the collapse of the digital eye beyond 40 Gbps. To counter this, Pulse Amplitude Modulation 4-Level (PAM4) is beginning to emerge in digital communications which allows for the same fundamental frequency to be used as NRZ while doubling the data rate by introducing two additional amplitude levels to the traditional 2-level encoding. This paper will address the implications of this change for wafer test and will explore the sensitivity of PAM4 to different types of loss along with how this loss can be countered in the probe card.

5G: The Phanerozoic Eon of Parallelism | Bock
Presented at TestVision 2021

5G has been pushing on wafer test of several years now and the test cell is evolving to more complex systems.  Same as the change to multicellular life during the Phanerozoic Eon, we are seeing a concerted change to multi-DUT testing with 5G parts in order to improve the output from manufacturing wafer test.  Now, 5G is in the middle of ramp, with more handsets being released with 5G FR2 chipsets being released. Current estimates put up to a 150.7% CAGR increase in the number of devices with 5G from now until 2024.  This growth requires a subsequent increase in the wafer test capability in the manufacturing flow to provide Known Good Die (KGD) in a reasonable cost of test.  There are multiple ways to increase the volume and minimize cost of test.  Some of these include more test cells, but buying more testers is can become cost prohibitive. Another strategy is to provide more test parallelism with upgraded testers that have mW frequency capability with a low number of channels in the tester, but resources are extended by using switches and other types of channel count increase.  Another method is to use wafer loopback test, but that reduces the test visibility due to the signals never getting back to the tester.  All of these have advantages and drawbacks.  We will discuss multiple ways to do this as well as discuss the Cost of Ownership Implications.

The Digital Revolution: NRZ to PAM4 | Bock, Raschko
Best Overall Presentation - SWTest 2021

With increasing demand to process more data and pass large amounts of data through servers, cellular devices, and even within the computer for the highest performing video cards, the need for more complex digital processing is becoming greater than ever. In this presentation, Daniel Bock and David Raschko will show some of the impacts of NRZ compared to PAM4 on wafer test through example probe cards and describe the changing test requirements.

Next Generation KGD Memory Test Achieved Wafer Level Speed Beyond 3 GHz/6 Gbps | Liao
Presented at SWTest 2021

Recent industry wide adoption of heterogeneous integrated system enabled by 2.5D and 3D advanced packaging technology is driving up the demand for known-good-die. Coupled with the advancement on DRAM and High Bandwidth Memory (HBM) native speed capability, the latest memory is running beyond 2 GHz (4 Gbps) which is pushing the limit on existing ATE testers. Recent joint effort between SK Hynix, FormFactor and Advantest successfully demonstrated that beyond 3 GHz is achievable. This session discusses the design challenges overcame in this collaboration from a system level signal integrity and power delivery perspective.

Next Generation SmartMatrix Probe Card Technology Enables 3000-Parallelism 1TD Test for 1Z DRAM Process Node | Ceremuga
Presented at SWTest 2021

The DRAM technology process node continues to shrink, driven by the demand to increase bit density and reduce memory device cost. With the recent accelerated transition from the 1Y to 1Z process node, die count per wafer is increasing rapidly. Wafer sort throughput must advance to achieve the target cost without adding significant capital expenditure to the existing test floor. Samsung and FormFactor have been working together, and successfully developed and qualified the next generation DRAM probe card that leverages FormFactor’s ATRE technology for 3000-parallelism and beyond. FormFactor’s SmartMatrix 3000XP probe card enables remarkable high-parallelism test throughput by extending ATE tester resource sharing up to X32. This session discusses the key technology enablers of the SmartMatrix 3000XP product architecture, and the design challenges overcame during this successful collaboration.

Challenges of Expanding Large Area Active Array for Fine Pitch Vertical Probe Cards | Harker, Desta
Best Data Presentation - SWTest 2021

Semiconductor manufacturers are on a relentless drive to reduce the total cost of test at sort. A major contributor to reducing cost of test is increasing simulations Device Under Test which requires a subsequent increase in the probe card active area. FormFactor has developed a new probe card architecture to address the challenges of fine pitch, high CCC, and high temperature range for wire bond probing applications.

2020

Test Setup Optimization and Automation for Accurate Silicon Photonics Wafer Acceptance Production Tests | Sia
Presented at ICMTS 2020
FormFactor’s Dr Choon Beng Sia with co-authors from GLOBALFOUNDRIES Singapore, present a technical paper on production testing of Silicon Photonics wafers at the 33rd IEEE International Conference on Microelectronic Test Structures (ICMTS). In the paper, they demonstrate incident angle optimization for optical wafer tests as well as evaluation of a fully automatic SiPh wafer test architecture that is accurate and dependable.

2019

2D MEMS Probe to Parametric Testing and Other Probe Technology | Saeki
Best Overall Presentation - SWTEST Asia 2019

In his paper, FormFactor’s Takao Saeki unveils Takumi CL, a new low-impact parametric MEMS probe card for low-leakage and small pad size applications. Featuring a new 2D MEMS spring and contact tip, the Takumi CL offers a consistent small scrub mark over the life of the product, with the benefits of low cost and fast manufacturing lead time.

Ultra High Temperature Probe Card Solution for Automotive IC Testing | LiaoIn this paper, we will discuss overall industry trend of automotive IC growth and technology trends, wafer test challenges and FromFactor’s solution to enable massive parallel testing of >=128 DUT parallel test on automotive micro-controller device, from -40C to 160C. We will also share extensive engineering characterization results on prober deflection and thermal behavior, high pin count probe card AOT vs. POT, low force MEMS probe on wafer pad to achieve zero defect IC wafer probing requirements.

Improving Wafer-Level S-parameters Measurement Accuracy and Stability with Probe-Tip Power Calibration up to 110 GHz for 5G Applications | Sia
This paper presents a novel method of probe-tip power calibration for S-parameters calibration which is shown to greatly improve DC biasing accuracy, S-parameters measurement accuracy and post-calibration stability up to 110 GHz.

Advanced Packaging, Heterogeneous Integration and Test | Slessor
Major products rely on advanced packaging to reach the market; a groundswell of die-integration technologies are revolutionizing packaging, assembly, and test.

Advanced Packaging - It's Changing the World of Wafer Test  Slessor
Presented at TestVision - Semicon West 2019

Automotive IC Production Wafer Test In a Zero-Defect World || Leong
Chip Scale Review asked FormFactor CMO, Amy Leong to respond to questions that provide insights into challenges associated with automotive IC production wafer testing amid the requirement for zero-defects.

Characterization of Micro-Bumps for 3DIC Wafer Acceptance Tests | Sia
Presented at ICMTS 2019

The strong market demands to embed different functionalities from various semiconductor processing technologies into a single system continue to drive demands for 3DIC, in particular, shrinking micro-bump sizes to facilitate stacking of multiple dies. Probecards and Single DC probes are unable to address the measurement flexibilities and challenges needed for micro-bump wafer acceptance tests. In this paper, custom DC positioners with theta-X planarizing capability and true Kelvin probes have allowed for successful demonstration of consistent and repeatable test results in fully automatic micro-bump wafer acceptance tests.

Silicon Photonics: Automated wafer-level probing meets silicon photonics | Frankel, Negishi, Simmons, Rishavy, Christenson
As chip designers are pressed for ever-increasing data rates, the use of wavelength-division multiplexing (WDM) with infrared photonic signals as a data transfer medium is increasingly finding its way into CMOS silicon-based devices. Termed “silicon photonics” (SiPh), this technology is not only being used to displace traditional electrical interconnects, but also for a broad range of applications, including lidar, quantum computing, and biosensing.

New test methodologies for 5G wafer high-volume production | Bock, Damm
Companies developing 5G technologies are racing to develop the first chipsets in order to set the standard of deployment and be the leader. While initial standards for 5G were set at the end of 2017, and there are ideas about the applications of 5G, it is still unclear how exactly it will all come together. This article explores the challenges and changes in test methodology of 5G devices, and showcases the results of a collaboration with Intel.

5G Wafer Test and the New Age of Parallelism | Bock, Sia
Best Overall Presentation - SWTEST 2019

The development of new RF devices (5G and high speed digital components) is changing the landscape for RF probing. For many years, RF probing in frequencies beyond cell phone and WiFi frequencies was a niche area, only requiring a very small number of lines as well as not meeting the needs for High Volume Manufacturing (HVM).

Silicon Photonics Challenges and Solutions for Wafer Level Production Tests | FormFactor & Global Foundries
Most Inspirational Presentation - SWTEST 2019

Data centers around the world currently consume about 7% of the earth’s total power output. To satisfy the increasing demands for cloud computing and support emerging applications such as artificial intelligence, genomics revolution and data analytics, hyperscale data centers are being built around the world at an accelerated pace, with analysts predicting up to 20% of earth's total power output consumed by data centers in 2030

High Density Probe Card PCBs - Are You Your Own Worst Enemy to Achieving Higher Parallelism on your Designs? | Powell, Ojeda
Best Presentation Tutorial in Nature - SWTEST 2019

As Probe Card PCB’s complexity, and net counts increase most customers are not paying enough attention to their Power/Channel assignments to make their High Density PCB Designs possible to manufacture. Compounding this issue are tester manufacturers that create Non-optimal Channel assignment restrictions on their testers. This further complicates your ability to achieve higher parallelism testing.

Hybrid MEMS Technology 2.0 | Kister, Leong, Bhardwaj
At 2017 SWTest workshop, Qualcomm and FormFactor introduced the innovative Hybrid MEMS probe technology for advanced probing application. Hybrid MEMS technology allows multiple probe designs to be used in a single probe head design, with each probe design optimized for a specific purpose. The technical innovation to enable Hybrid design is to leverage multi-layer composite MEMS fabrication technology, which allows the optimal wafer test performance by including otherwise mutually exclusive requirements such as fine-pitch and high current carrying capability.

Improving Signal Fidelity in High Parallelism Probe Card via TTRE | Young-woo, Quay
With DRAM process node transitioning to 1X, 1Y, and 1Z, die shrinkage is driving die per wafer to the level of 2000 device or more. Wafer test using a single touchdown probe card is inevitable and can be achieved using tester resource enhancement without having to spend an excessive amount of capital expenses to upgrade existing ATEs.

Probing 5G Devices Like Its No Big Deal | Lesher, Rhodes
The rollout of 5G networks is in its infancy, but the demand for 5G devices is already here. Those devices will be in consumer products like phones, but they’ll also be integrated into new infrastructure all around us – and volumes will be hefty as a result. As with any high volume ICs, comprehensive, multi-site testing at the wafer level offers the lowest cost of test, but 5G devices have challenges not seen before in volume production. The need to support many tens of signals in the many tens of GHz range is in fact a big deal.

A Fully Automatic Electro Optical Test System Enabling the Development of a Silicon Photonics Technology Platform | FormFactor & imec
A fully automatic system for wafer-level testing of photonic devices is presented. The test system is deployed for optical process control monitor (PCM) characterization to support the ongoing development of a silicon photonics technology platform.

Tools and Techniques for Validation of VNA Calibrations with Wafer Microprobes | Kirkpatrick

Improving Probe-Tip S-parameters Measurements with Power Calibrations | Sia

2014

Cost Effective 1,000V High Voltage Parametric Test Technique | Andoh, Ishibiki, Kawamata, Funatoko

Advance Low Force Probe cards Used on Solder Flip Chip Devices | Stillman, Hughes

Key Considerations to Probe Cu Pillars in High Volume Production | Wittig, Leong, Nguyen, Masi, Kister, Slessor
Winner of “Best Overall Presentation”

Can Testers and Probe Cards Keep Up With Speed Requirements for Image Sensors? | Levy, Kawamata, Hamajima

International Technology Roadmap for Semiconductors | Armstrong, Feldman, Loranger

2006

One Touch 300mm Wafer Probing | Wijeyesekera, Shinde