Technical Papers

2024

Quantum Computing IC Die-Level Test Solution in mK-Temperature Environment | Liao, Dai, Takuji
Presented at SWTest Asia 2024
Cryogenic microelectronics, including Cryo CMOS, superconducting devices, and quantum computing chips, is rapidly advancing, driving demand for innovative test and measurement solutions in ultra-low-temperature environments. FormFactor’s PQ500 offers a groundbreaking, cryostat-agnostic socket interface with high-density RF and DC channel capacity, eliminating the need for wire bonding or packaging.

This presentation will showcase the PQ500's key application, developed with Prof. Miki from Kobe University, and present electronic characterization data from a typical PQ500 setup in cryogenic conditions. We will also outline the future roadmap for the PQ500 and other FormFactor solutions advancing cryogenic testing technologies.

Narrow Pitch Impedance Standard Substrates (ISS) for Pyramid Probe Applications | Ghate
Presented at SWTest 2024

The growth of Large Language Models (LLMs) like ChatGPT, BING AI, and Google BARD/Gemini has led to a rapid increase in demand for faster and more efficient optical communication. To meet this need, operating frequencies and bandwidths must increase, driving demand for more integrated and compact solutions. This manifests in the need for higher data rates in IO devices (such as transimpedance amplifiers (TIAs), laser diodes, etc.) to enable real-time communication, ensure scalability, and improve system efficiency and performance, thereby making higher data rates essential to meeting the evolving demands of applications driven by LLMs. To ensure high DUT yield, wafer tests at >=60 GHz are essential to validate IO devices capable of achieving these higher data rates. Pyramid Probes provide high-quality device under test (DUT) characterization in wafer tests beyond 67 GHz in high-volume manufacturing (HVM) environments, making them an ideal solution for this need. As DUT size decreases, pitch follows suit, with a drive to pitches <100 um. These narrow pitches provide various advantages such as a reduction in parasitic capacitance and inductance and enable increased device density necessary for advanced packaging technologies solutions. In this paper, we will discuss the impact of narrower pitches and smaller pad dimensions on DUT characterization in the context of ISSs. We will review the challenges of signal coupling and signal crosstalk that affect signal integrity, and other strategies for reducing calibration standards sizes and their impacts on various calibration methods.

Risk Mitigation Strategies for mmWave Production Test | Ayers, Garrison
Best Presentation at SWTest 2024

With the 5G mobile network in full deployment, antenna transceivers operating in the 24.25 GHz to 43.5 GHz frequency bands have become integral components of high-end smartphones. These transceivers utilize advanced beam steering and beamforming techniques to optimize wireless data transmission, necessitating precise phase control across up to 32 RF signals. Ensuring these chips are verified as Known Good Die prior to module integration is crucial, demanding probe cards and testing equipment that deliver laboratory-grade precision in RF measurements at production scales. Employing membrane-based probe technologies meets the electrical demands which result in higher forces, necessitating meticulous setup and system deflection management to ensure optimal contact performance and durability. This challenge is further compounded when scaling test parallelism to reduce the Cost of Test. For instance, with an eight-site probe head configuration, there are hundreds of nets, nearly a third of them being RF signals, interacting through approximately 5000 probe contacts, and resulting in 50-80 kg of probing force. This presentation delves into several strategies and the utilization of specific equipment to gather empirical data on Actual vs. Programmed Overtravel in multi-site RF probe cards. We will explore how this data informs the development of baseline models for predictive Finite Element Analysis modeling, paving the way for enhancements in future applications. These methodologies mitigate some of the prevalent risks associated with mmWave chip testing in high-volume manufacturing contexts, ultimately contributing to a reduction in the overall Cost of Test

Optical Edge Coupling Method for Fully Automated PIC Wafer-Level | Rishavy
Presented at SWTest 2024

As the field of silicon photonics applications expands, so does the demand for high-throughput optical on-wafer testing of photonic integrated circuits (PICs). The well-known grating couplers used for many years for on-wafer testing have many drawbacks such as high polarization dependence, reduced bandwidth, and relatively low coupling efficiency. Recently, the edge coupler has become a prominent candidate for photonic foundries as a coupling interface to the chip. The low polarization dependence, low coupling loss, and compatibility with advanced packaging solutions make this interface very attractive for many applications. However, testing on the wafer level using edge coupling has lagged behind grating coupler-based probing due to the complexity of the method and problems that need to be overcome. The calibration automation was always complex and heavily dependent on the skills of the operator. In recent years, there have been some concepts and experiments in the literature regarding edge coupling on the wafer level. To date, though, a fully automated solution has not been demonstrated. In this presentation, we would like to demonstrate the fully automated turnkey solution that has been developed by FormFactor Inc. We will provide an overview of the system and show repeatability results obtained on a 200 mm photonic wafer. We propose an alternative optical probing technique suitable for automated on-wafer measurements based on edge coupling, but that can also be used for surface coupling. Here, we evaluate a solution based on FormFactor’s CM300-SiPh probe station and the Pharos Probe. A brief overview of the system is given, and the repeatability of the coupling across the wafer is investigated. The solution is suitable for a wide range of photonics test requirements. The overall system is based on a fully automated Probe Station (FormFactor CM300xi) with an advanced eVue machine vision-based microscope system and 6-axis optical positioner (based on PI HexaPod H-811 and NanoCube P-611.3). The optical probe is a fiber array with optical lenses and will be described further in the presentation. The automated algorithm calibrates and moves the optical probe in Y and Z directions to find the maximum signal intensity and thus the best coupling point.

Advanced Probe Card Solutions to Address HBM Wafer and Stacked Die Test Challenges | Cooke, Ghosh
Presented at SWTest 2024

Advanced Packaging has evolved significantly over the last few years. High Bandwidth Memory has emerged as the leading revenue growth opportunity for Memory Manufacturers, with 2.5D and 3D package technologies. This discussion is focused on problems Memory Manufacturers face when utilizing probe cards to ensure Known Good Die (KGD) test. Millions of bits are exchanged from GPU to Memory Stacks (9.6 GT/s (gigatransfers per second)) with HBM3e. This dynamic is demanding more power and the ability to handle heat dissipated by each new HBM version, each with an increased number of stacked die which in turn will result in problems for the probe card to withstand this heating and provide stable probe-to-pad alignment. In order to respond to these challenges, we will discuss thermally scaled MEMS technology for sorting and KGD.

Making Accurate and Consistent Wafer Measurements with Next Generation Guarded True-Kelvin MEMS DC | Sia
Presented at ICMTS 2024

Gate length down-scaling of silicon-based transistor results in very small on-state drain-source resistance, making it challenging for test engineers to perform precise and repeatable wafer measurements. Size reduction of aluminumcapped copper test pads to save on lithography, prototyping and production costs implies that it is very difficult to re-probe the same device with low contact resistance. Novel true-Kelvin MEMS analytical DC probes, new test and modelling strategies are proposed in this paper to address these emerging test challenges.

2023

Complex Impedance Matching Structures for Advanced On–Wafer AiP Testing | Ghate
Presented at SWTest Asia 2023

The growing demand for more integrated and miniaturized solutions in modern wireless communication systems is driven by the increasing frequency of operation and operational bandwidths. One significant development in this direction is the integration of antennas directly onto the chip or within the package of the wireless device. This concept is known as "antenna-on-chip" (AoC) or "antenna-in-package" (AiP). The integration of antennas (either AoC or AiP) in the package provides numerous advantages, including the reduction of parasitic effects, improved electromagnetic performance, improved efficiency, miniaturization of the system, simplified design, etc. In this work, we present complex impedance matching structures embedded in FormFactor's Pyramid Core that will play a major role in improving wafer test coverage with better yield and lower cost of ownership (COO) as immediate benefits.

Current Carrying Capacity Maximization in Probe Cards and the Path to An Unburnable Probe | Najar
Presented at SWTest Asia 2023

Data centers and High-Performance-Compute (HPC) applications are quickly approaching, and even exceeding, 1 kW of total power in a single chip under normal operating conditions. In addition to new applications, the transition to new nodes further increases the total power per unit area in a semiconductor, which compounds the challenge of increased power and thermal output of a device during testing, even in low-power consumption applications such as mobile application processors. This continuous increase in device output power creates several challenges regarding wafer testing, particularly in maintaining contactor integrity at high current and in high-temperature environments. To address this trend, higher CCC in the probe during testing must advance at a rate similar to the increased power observed in the DUT, leading to increased uptimes and lower cost of testing. This paper will discuss several techniques that can be utilized in the probe card to maximize CCC and achieve an effective CCC of >2.5 A in a probe card at an 80 um minimum pitch. These techniques include both new probe developments and architectural improvements to maintain probe integrity in a high-stress, high-current environment.

Maximizing Return on Investment for On-Wafer Over Temperature Millimeter Wave Characterization | Fisher
Industry Workshop at IMS 2023

The presentation will demonstrate the best practices for configuring, calibrating, and assessing measurement performance across a wide frequency range, from WR15 (75 GHz) to WR1 (1100 GHz), and in a broad temperature range (-40 to 125°C). This will include methods for conveniently switching between different waveguide bands.

Dynamic Height Adjustment Using Vector Network Analyzer-Based Contact Sensing Using FormFactor WinCal XE 4.9 ™ and Velox 3.4 | Fisher, Hibbert
MicroApps Seminar at IMS 2023

For testing at mmWave frequencies, the tolerances for final probe positioning are critical. The Z variation from the substrate to the probe tip can significantly contribute to positioning errors, possibly due to unintended contaminants on the rear of the substrate that affect its flatness. Accurate contact can be precisely determined using mmWave spot measurements. By utilizing Formfactor WinCal XE calibration software and Python scripting in conjunction with our Velox prober control software, we can eliminate these Z variations by sensing contact and making real-time adjustments. We will provide examples of Python scripting and a video demonstrating a real-life calibration that incorporates dynamic Z adjustment.

On Membrane Attenuators for 60 GHz Loopback Transceiver Testing | Nelson
Presented at SWTest 2023

On-wafer testing of transceivers often requires feedback configurations where the transmitters output is fed back into the receiver. Because of this, there is a need to attenuate the feedback signal to avoid saturation of the receiver. Traditionally, this has been achieved by feeding the signal to a coaxial attenuator and then fed back into the receiver. A new solution has been developed which replaces the coaxial attenuator with on-membrane attenuation structures.

Quantum and CryoCMOS :Enabling the Future of Computing with Advanced Test & Measurement Tool | DeGrave, Boiko
Presented at TestVision 2023

Advanced computing and quantum computing devices require cryogenic conditions for the processor itself as well as the control chips that drive microwave signal to the processor. These advanced devices typically include niobium or aluminum superconducting circuits, and their support chips are based on cryogenic compatible CMOS structures. Bringing this new technology from the research and development phase, out of the lab and into engineering scale production and ultimately volume production requires specialized tools to test, measure, and deploy the advanced devices all in sub-4K environments. The major bottlenecks include time-consuming wire bonding, expensive packaging processes prior to device cooldown, and long cooldown times for dilution refrigerators. FormFactor is the leading enabler of quantum computing developers with its suite of cryogenic test and measurement tools as well as deployment solutions. We discuss a customer case study implementing cryogenic wafer probing on SFQ circuits to obtain statistical datasets in hours that would otherwise take weeks or months, a new tool for rapid die testing that makes use of a cryogenic high-density MEMS probe head, enabling photonics probing below 2K, and the deployment of quantum devices in milli-Kelvin dilution refrigerator cryostats with a probe socket interface.

Advancing Probe Card Parallelism for SOC Devices | Harker
Presented at TestVision 2023

The demand for semiconductor devices continues to increase at an unrelenting pace. Integrated circuits are in more and more of the products and services we use and interact with in our everyday lives. One segment of particular interest is the automotive semiconductor market. Semiconductor device content is increasing from an average of $400 per standard automobile to over $1,100 for battery electrified vehicles. This increase in the semiconductor content causes additional pressure on the semiconductor suppliers to further reduce device costs.

One approach to reducing the device costs is to reduce the cost of test of the devices. In order to reduce the cost of test for automotive devices, Infineon worked with FormFactor to implement the production proven TrueScale Matrix platform for the V9300 direct dock tester. The TrueScale Matrix product had previously been deployed into production on traditional round PCBA tester configurations. Working together, the initial configuration was developed in a rectangular probe head configuration providing an active area to 200mm by 300mm resulting in a significant increase in the probe card parallelism and reducing the overall cost of test. An additional enhancement to the probe card architecture enabled a 300mm full wafer contactor solution to further increase the parallelism and test efficiency.

This presentation will review the results of the collaboration between Infineon and FormFactor to implement the high parallelism TrueScale Matrix product solution on V93000 direct dock tester systems. In addition, superior thermal mechanical design of the probe card provides a capability to use same probe card over wide temperature range from -40oC to 150oC. We will also share extensive engineering characterization results on prober deflection and thermal behavior, high pin count probe card AOT vs. POT and the low force MEMS probes on wafer pad to achieve stable contact over the large probing array with minimal impact to the test pad.

Production Test RF Calibration Methods for Probe Cards | Ghate, Bock
Presented at TestVision 2023

During RF measurement in production environments, the increased accuracy required for Known-Good-DUT requires RF calibration to the probe tip. This is due to the higher bandwidths and higher channel counts for semiconductors chips that are supporting 5G FR2 and as well as chips that are moving data in and out of large data centers. However, calibration substrates in general have not been designed to provide the best measurements possible due to the unique layouts of these devices. This can be attributed to the un-controlled RF state of the non-measured channels interacting with the channels that are being measured as well as the limitations due to the types of RF calibration algorithms that are available for HVM wafer test at RF. I will review some design methodologies for making the calibration substrates, as well as which RF calibration methods are best for the particular layout. In addition, I will present example RF measurements of these different situations that can be used for calibration verification prior to wafer test.

Maximizing CCC and the March to an Unburnable Probe | Raschko, Najar
People’s Choice Award and Best Data Presentation – SWTest 2023

Data centers and High-Performance-Compute (HPC) applications are quickly approaching and even exceeding 1kW of total power in a single chip in normal operating conditions. In addition to new applications, the transition to new nodes further increases the total power per unit area in a semiconductor, which compounds the challenge of increased power and thermal output of a device during test in even low-power consumption applications such as mobile application processors. This continuous increase in device output power creates several challenges regarding wafer test, particularly with maintaining contactor integrity at high current and in high-temperature environments. To combat this trend, higher CCC in the probe during test must advance in a rate similar to the increased power being observed in the DUT leading to increased uptimes and lower cost of test. This paper will address several techniques that can be utilized in the probe card to maximize CCC to achieve an effective CCC of >2.5A in a probe card at a 80um minimum pitch including both new probe developments along with architectural improvements to maintain probe integrity in a high-stress, high-current environment.

Scaling Measurement Methodologies Using Cryogenic TaaS Framework for Higher Quality Cryo LNAs and Reliable Qubit Readout Chains | Boiko
Technical Workshop at IMS 2023

As superconducting quantum computers scale, cryogenic microwave components in the qubit control and readout chain must be appropriately tested and qualified to ensure the consistency and high fidelity of quantum computation. Furthermore, system uptime is critical for commercialization, which is dependent on reliably predicting maintenance cycles and expediting downtime recovery. Both requirements highlight the need for standardized measurement protocols to scale the test capability in the industry. Here we will examine a test framework where we describe procedures for conducting functional, reliability, and integrated testing on cryogenic components. Our pilot use-case investigates calibration and test methodologies for gain and noise figure measurements of low temperature LNAs. Finally, we will discuss how to scale these measurements for high volume reliability testing.

Fully Automated Integrated Silicon Photonic Wafer Test | Rishavy
Presented at SWTest 2023

Integrated silicon photonics has found extensive use in modern high speed optical links. These optical transceivers are composed of various structures which require extensive passive, DC, RF, and electro-optic characterization at wafer level. A high degree of automation in addition to minimal reconfiguration of the test setup is necessary to improve test throughput. Herein we discuss the use of the CM300 silicon photonics probe station to enable automated full wafer characterization of various passives, DC electro-optic, and VNA measurements of thermal phase shifters, modulators, and photodetectors. FormFactor’s Pharos technology that enables industry proven wafer level automated edge coupling test capability will also be described.

Considerations for Vertical High Probe Count | Martin
Presented at SWTest 2023

As semiconductor suppliers strive to increase their throughput and lower their test costs, probe card parallelism continues to increase. State of the art probe card designs require up to 80,000 probes and the industry is driving for as much as 150,000 probes in the future. Where are the limitations? Total probe force will be >200 kgf and while there are testers that can handle this amount of force, probe card deflection needs to be considered to maintain high volume production requirements. Today, the ratio of actual overtravel on the probes to the programmed overtravel can be as low as 30% which makes achieving low contact resistance between probe tip and wafer a challenge. Increasing probe card stiffness is simple in theory but the space constraints between probe card and tester plus the need to populate the PCB with many components makes this very difficult to achieve. In addition to the tester, the prober and probe card metrology tools will need to accommodate this higher force as well. This paper will provide a survey of the test equipment industry and identify the chief limitations including where probe card mechanical design needs to improve

Pyramid Probe: RF Calibration and Probe Aging Considerations in HVM High Speed IO | Bock
Presented at SWTest 2023

The growth in AI (such as ChatGPT and BING AI) is requiring large investments into the expansion of data centers, driving higher and higher data rates in IO devices. To reach these data rates, wafer test is moving to bandwidth > 60 GHz. Pyramid Probes are widely used for wafer test at up to 81 GHz and in high volume manufacturing (HVM). These probes feature micro-strip or CPW transmission lines that provide controlled impedance and low loss (<6 dB at 67 GHz) for the industry leading performance at wafer test. However, in the standard layout, the signal trace faces the wafer and is only 70 um away, so that it can sometimes couple to structures on the wafer. This coupling can have significant effects in some cases, in both DUT performance and RF calibration of the probe head. Further, one expects the coupling to increase as the probe ages and the tips become shorter, bringing the microstrip closer to the wafer. To reduce this coupling, Pyramid Probes using a microstrip with the ground between the transmission line and the wafer (inverted microstrip) are available. In this study, we will use probes with standard and inverted microstrips to measure TIA (transimpedance amplifier) performance. Measurements before and after aging the probes will be compared to characterize these effects. In addition, we will look at different calibration methods (SOLR, SOLT, SOL de-embed) and compare them to provide recommendations for calibration.

2022

Achieving Traceable RFCMOS F_T and F_MAX Wafer Measurements | Sia
Technical Presentation at APMC 2022

This paper investigates the impacts of RF probe aging, how RF probe contact resistances on test pads of calibration
standards and devices affect the Ft and Fmax measurements of RFCMOS transistors. A RF wafer test strategy to help device and test engineers
obtain accurate, repeatable and traceable Ft and Fmax measurements is proposed at the end of this paper.

A Guide to Full Autonomous Operation Using MLTRL Calibration on and off the Wafer | Fisher
MicroApps Seminar at IMS 2022

FormFactor has previously shown the Autonomous RF Measurement assistant using LRRM Calibration. Autonomous RF is used to manage the entire test flow for thermal and ambient testing. This includes the full automated calibration, monitoring to prevent measurement drift, adjustment of probe spacing to account for growth and adjust probing geometries to deal with devices of different layout. In this talk, we will discuss the use of this approach with regard to doing MLTRL calibrations with this approach instead both off and on wafer. We will also show interaction between WinCal, python and analytical approach to evaluate the calibration repeatability.

Fully Automatic 4K Cryogenic Probe Station for DC and Microwave Measurements on 150mm and 200mm Wafers | West
Technical Presentation at IMS 2022

Robust maturation of cryogenic electronics has been limited by the lack of high-throughput measurement capabilities, especially for electronics that operate at 4 K. Automated on-wafer probing to characterize the dc and RF performance of components and complete circuits has been a critical element in the development of room temperature electronics. We report here the development of a fully automated wafer prober that operates with the wafer cooled to a temperature of 4 K and has the ability to null the ambient magnetic field to below 100 nT, which is important for measuring superconducting circuits with the wafer prober.

Accelerated Solid State Qubit Pre-Screening | DeGrave
Industry Workshop at IMS 2022

Until recently, quantum engineers operating devices at milli-Kelvin temperatures are faced with the difficulties and inconveniences of long development cycles The major bottlenecks include time-consuming wire bonding, expensive packaging processes prior to device cooldown, and long cooldown times for dilution refrigerators This workshop presents an integrated measurement solution for Pre-Screening qubit devices, allowing quantum engineers to eliminate wire-bonding and packaging from cryogenic test processes and to provide critical qubit performance parameters at 50 mK, thus streamlining device deployment, and reducing the time for development cycles

Single Sweep Broadband S-Parameter Measurements to mm-Wave for Semiconductor Transistor and IC Test to 220 GHz | Fisher
MicroApps Seminar at IMS 2022

Measurements beyond conventional coaxial limits often means more frequent changes to the banded setup. For some time there have been requests to enable measurements to go all the way to 220 GHz in a single sweep with performance levels equivalent to conventional coaxial approaches. In this presentation we will show the new optimized single sweep solution with some initial measurements. We will also present typical analytical approaches to evaluate the performance of the system using python and WinCal. We will also show the new storage pod design to enable quick and safe band swaps if needed beyond 220 GHz.

Broadband over Temperature Measurement Optimization for on Wafer Test | Fisher
Industry Workshop at IMS 2022

We will highlight the best methods for setting up, calibrating, and evaluating measurement performance in coaxial and waveguide bands spanning WR15 (75 GHz) to WR1 (1100 GHz) over a broad (-40 to 125c) temperature range
A novel out single sweep measurement from 900 Hz to 220 GHz will be shown along with detailed complete automation of these measurements. Many programming examples using WinCalXE software will be demonstrated automating data measurement and analysis for on wafer measurements. We also evaluate system stability and performance. A very convenient approach is discussed to allow safe and convenience band swaps and probe installation.

Strategies for Enabling Quantum Development with Test and Measurement from 77K down to milli-Kelvin | DeGrave
MicroApps Seminar at IMS 2022

Quantum computing will likely utilize numerous new technologies which operate at different cryogenic temperatures. For example, a quantum computer might deploy CMOS memory modules at 77 K, superconducting control chips at 4K, and a quantum processing unit (QPU) at less than 20 mK. To develop and deploy these various subsystems and technologies, it is vital to reliably and efficiently test and measure them at or near their operating temperatures.

Next Generation DRAM Temperature Requirements and Impacts to Full Wafer Contactor Probe Card | Lee
Presented at SWTest 2022

Traditional DRAM devices for server, mobile and commercial application require wafer test temp range from -25oC to 10oC for cold, up to 85oC to 105oC for hot test. Emerging new devices for automotive, industrial and military applications require increased test temp range from -40oC to 125 oC and higher. DRAM probe card solutions for volume production are based on 300mm, full wafer contact architectures to support 1TD solutions. Expansion and contraction of the 300mm wafer for these increased temperature ranges create significant challenges for full wafer contactor probe cards including CTE matching to the movement of the full 300mm wafer. In addition, requirements are trending for smaller pad pitch and smaller pad size increases the probing challenges to be solved. Probe card solutions not only need to satisfy the challenges of reduced pad pitch, pad size and increase temperature range but also must consider PCB component selection and strategic component placement, chuck movement time and strategies to maintain probe card thermal stability. This presentation will review emerging market drivers, impacts to probe card requirements/challenges and 300mm full wafer contactor solutions.

5G mmWave: Multi-site RF Probe Cards Enable Lower Cost-of-test in Mass Production | Garrison
Presented at SWTest 2022

5G mmWave systems are here. Advanced Antenna-in-Package modules and RFFE chipsets are integral to the latest generation of high-end smartphones and tablets, and this capability is becoming more ubiquitous in 2022. These chips, containing a massive amount of mmW content, are ramping in mass production, and the companies producing them need a way to reduce cost of RF test. To realize actual cost reduction, tester and probe card companies need to evolve quickly to support increased parallelism of mmWave testing. This session drills down into the RF test cell to examine enhancements enabling increased parallelism using new probe head architectures.

Advances in Vertical Probing for High-speed Digital Test at Wafer Sort | Raschko
People’s Choice Award – SWTest 2022

Digital communication speeds are rapidly increasing through PCIe standards, Ethernet standards, and OIF/CEI standards. This increase in data rate leads to significantly higher system or module losses and these losses must be accounted for in the TX and RX channels of a die. To account for channel loss, equalization is used where the digital signal is altered in a manner that removes the effects of the channel loss. As this equalization becomes more prevalent throughout the semiconductor industry, wafer test methods will need to be created that will enable the testing and application of the channel equalization inherent to the device under test. This will require probe cards to emulate the loss profile of the expected channel for which the device under test is designed for in order to properly exercise the channel equalization of the die. This paper will go over the inherent challenges of replicating system loss in a probe card, methods of matching expected system loss, and the implementation of novel probe card design features that enable proper exercising of a die’s channel equalization during wafer sort.

High Speed Digital: How to Optimize a Probe Card for PAM4 Signaling to a non-50 Ω | Bock
Best Data Presentation – SWTest 2022

The release of the 5G standard and the expansion of broadband internet is steadily increasing the load on the data communication infrastructure. The data communication infrastructure operates over fiber, and is using PAM4 modulation, moving from 28 Gbps to 56 Gbps (and beyond). For wafer test, this translates to test requirements at very high speeds and in some cases outside of the typical 50 ohm environment. Transimpedance Amplifiers and the associated Laser Drivers in the fiber communication chain are typically not connected to a 50 ohm device (in this case a photodiode or a laser driver , respectively). Due to this distinction, they typically have port impedances that require broadband matching between the device under test and the tester 50 ohm environment in order to pass a digital signal. We’ll examine the advantages of putting a matching circuit on the probe card specifically tuned to the impedance of the photodiode (for example), which typically operate at non-50 ohm. We will talk about the work done in optimizing the performance of a probe card in order to maximize the eye in a PAM4 signal. This includes both component selection, as well as optimization of the traces on the Pyramid Probe. In particular, making sure that the components are as close to the device under test is critical to maintain the best performance possible. We will also present simulated eye diagrams that would be seen at the tester, to show the performance improvements due to the tuning of the circuits to maximize eye height and width of a PAM4 signal.

Probecard Challenges for Expanding Arrays of Fine Pad Pitch Devices to Test Under Wide Temperature Range | Dastmalchi
Presented at TestVision 2022

A major contributor to reducing cost of test is increased simulations of the Device Under Test which requires a subsequent increase in the probe card active area. For wire bond applications, increasing the active area must also meet the requirements of an extremely wide temperature range, very fine pitch and electrical performance. These factors, along with other considerations, increases the probe card design complexity exponentially.

5G Mmwave: Multi-site RF Probe Cards Enable Lower Cost-of-test in Mass Production | Garrison
Presented at TestVision 2022

Advanced Antenna-in-Package modules and RFFE chipsets are integral to the latest generation of high-end smartphones and tablets. These chips, containing a massive amount of mmW content, are ramping in mass production, and the companies producing them need ways to reduce the cost of RF test. To realize actual cost reduction, tester and probe card companies need to evolve quickly to support increased parallelism of mmWave testing.

2021

Too Hot to Test for Leading-edge SoC and Heterogenous Integrated IC Stack | Leong
Presented at TestVision 2021

Leading-edge AI/Graphic/mobile processors, DRAM devices, and heterogeneous integrated IC stacks are all facing the same set of thermal management challenges -- the DUT is too hot to test. Even at room temperature wafer chuck setting, a mobile SoC device junction temperature can get well above 100 to 150C. For DRAM full-wafer testing, 1-2K watts of power could be applied during 1-TD testing, posting challenges for test cell thermal management. This results in inaccurate test results or frequently burned probes which cause test cell downtime. As the heterogeneous integration becomes more popular, the thermal challenges to test the base-die with multi-chips stacked on top further exuberate as the thermal loading per silicon area can increase by order of magnitude. You can’t improve what you can’t measure. FormFactor latest low-thermal-resistance (LTR) wafer chuck technology applies multiple temperature sensors to accurately detect DUT temperature and adjust heat dissipation to achieve the desired test temperature. LTR has shown promising results in production test to address the too hot to test challenge.

Next Generation KGD Memory Test Achieved Wafer Level Speed Beyond 3GHz | Lee
Presented at TestVision 2021

Recent industry wide adoption of heterogeneous integrated system enabled by 2.5D and 3D advanced packaging technology is driving up the demand for known-good-die (KGD) and known-good-stacked-die (KGSD). Coupled with the advancement on DRAM and High Bandwidth Memory (HBM) native speed capability, the latest memory is running beyond 2GHz (4Gbps) which is pushing the limit on existing ATE testers. Recent joint effort between SK Hynix, FormFactor, and Advantest successfully demonstrated that beyond 3GHz is achievable. This session discusses the design challenges overcame in this collaboration from a system level signal integrity and power delivery perspective.

Digital Revolution: PAM4 Wafer Test | Raschko
Presented at TestVision 2021

As data rates continue to increase, the difficulty of increasing clock rates for improved bitstreams becomes more challenging with ever-increasing loss. As of today, Non-Return-to-Zero (NRZ) is the standard for digital encoding, but this begins to run into problems with loss and the collapse of the digital eye beyond 40 Gbps. To counter this, Pulse Amplitude Modulation 4-Level (PAM4) is beginning to emerge in digital communications which allows for the same fundamental frequency to be used as NRZ while doubling the data rate by introducing two additional amplitude levels to the traditional 2-level encoding. This paper will address the implications of this change for wafer test and will explore the sensitivity of PAM4 to different types of loss along with how this loss can be countered in the probe card.

5G: The Phanerozoic Eon of Parallelism | Bock
Presented at TestVision 2021

5G has been pushing on wafer test of several years now and the test cell is evolving to more complex systems. Same as the change to multicellular life during the Phanerozoic Eon, we are seeing a concerted change to multi-DUT testing with 5G parts in order to improve the output from manufacturing wafer test. Now, 5G is in the middle of ramp, with more handsets being released with 5G FR2 chipsets being released. Current estimates put up to a 150.7% CAGR increase in the number of devices with 5G from now until 2024. This growth requires a subsequent increase in the wafer test capability in the manufacturing flow to provide Known Good Die (KGD) in a reasonable cost of test. There are multiple ways to increase the volume and minimize cost of test. Some of these include more test cells, but buying more testers is can become cost prohibitive. Another strategy is to provide more test parallelism with upgraded testers that have mW frequency capability with a low number of channels in the tester, but resources are extended by using switches and other types of channel count increase. Another method is to use wafer loopback test, but that reduces the test visibility due to the signals never getting back to the tester. All of these have advantages and drawbacks. We will discuss multiple ways to do this as well as discuss the Cost of Ownership Implications.

The Digital Revolution: NRZ to PAM4 | Bock, Raschko
Best Overall Presentation - SWTest 2021

With increasing demand to process more data and pass large amounts of data through servers, cellular devices, and even within the computer for the highest performing video cards, the need for more complex digital processing is becoming greater than ever. In this presentation, Daniel Bock and David Raschko will show some of the impacts of NRZ compared to PAM4 on wafer test through example probe cards and describe the changing test requirements.

Next Generation KGD Memory Test Achieved Wafer Level Speed Beyond 3 GHz/6 Gbps | Liao
Presented at SWTest 2021

Recent industry wide adoption of heterogeneous integrated system enabled by 2.5D and 3D advanced packaging technology is driving up the demand for known-good-die. Coupled with the advancement on DRAM and High Bandwidth Memory (HBM) native speed capability, the latest memory is running beyond 2 GHz (4 Gbps) which is pushing the limit on existing ATE testers. Recent joint effort between SK Hynix, FormFactor and Advantest successfully demonstrated that beyond 3 GHz is achievable. This session discusses the design challenges overcame in this collaboration from a system level signal integrity and power delivery perspective.

Next Generation SmartMatrix Probe Card Technology Enables 3000-Parallelism 1TD Test for 1Z DRAM Process Node | Ceremuga
Presented at SWTest 2021

The DRAM technology process node continues to shrink, driven by the demand to increase bit density and reduce memory device cost. With the recent accelerated transition from the 1Y to 1Z process node, die count per wafer is increasing rapidly. Wafer sort throughput must advance to achieve the target cost without adding significant capital expenditure to the existing test floor. Samsung and FormFactor have been working together, and successfully developed and qualified the next generation DRAM probe card that leverages FormFactor’s ATRE technology for 3000-parallelism and beyond. FormFactor’s SmartMatrix 3000XP probe card enables remarkable high-parallelism test throughput by extending ATE tester resource sharing up to X32. This session discusses the key technology enablers of the SmartMatrix 3000XP product architecture, and the design challenges overcame during this successful collaboration.

Challenges of Expanding Large Area Active Array for Fine Pitch Vertical Probe Cards | Harker, Desta
Best Data Presentation - SWTest 2021

Semiconductor manufacturers are on a relentless drive to reduce the total cost of test at sort. A major contributor to reducing cost of test is increasing simulations Device Under Test which requires a subsequent increase in the probe card active area. FormFactor has developed a new probe card architecture to address the challenges of fine pitch, high CCC, and high temperature range for wire bond probing applications.

2020

Test Setup Optimization and Automation for Accurate Silicon Photonics Wafer Acceptance Production Tests | Sia
Presented at ICMTS 2020
FormFactor’s Dr Choon Beng Sia with co-authors from GLOBALFOUNDRIES Singapore, present a technical paper on production testing of Silicon Photonics wafers at the 33rd IEEE International Conference on Microelectronic Test Structures (ICMTS). In the paper, they demonstrate incident angle optimization for optical wafer tests as well as evaluation of a fully automatic SiPh wafer test architecture that is accurate and dependable.

2019

2D MEMS Probe to Parametric Testing and Other Probe Technology | Saeki
Best Overall Presentation - SWTEST Asia 2019

In his paper, FormFactor’s Takao Saeki unveils Takumi CL, a new low-impact parametric MEMS probe card for low-leakage and small pad size applications. Featuring a new 2D MEMS spring and contact tip, the Takumi CL offers a consistent small scrub mark over the life of the product, with the benefits of low cost and fast manufacturing lead time.

Ultra High Temperature Probe Card Solution for Automotive IC Testing | LiaoIn this paper, we will discuss overall industry trend of automotive IC growth and technology trends, wafer test challenges and FromFactor’s solution to enable massive parallel testing of >=128 DUT parallel test on automotive micro-controller device, from -40C to 160C. We will also share extensive engineering characterization results on prober deflection and thermal behavior, high pin count probe card AOT vs. POT, low force MEMS probe on wafer pad to achieve zero defect IC wafer probing requirements.

Improving Wafer-Level S-parameters Measurement Accuracy and Stability with Probe-Tip Power Calibration up to 110 GHz for 5G Applications | Sia
This paper presents a novel method of probe-tip power calibration for S-parameters calibration which is shown to greatly improve DC biasing accuracy, S-parameters measurement accuracy and post-calibration stability up to 110 GHz.

Advanced Packaging, Heterogeneous Integration and Test | Slessor
Major products rely on advanced packaging to reach the market; a groundswell of die-integration technologies are revolutionizing packaging, assembly, and test.

Advanced Packaging - It's Changing the World of Wafer Test Slessor
Presented at TestVision - Semicon West 2019

Automotive IC Production Wafer Test In a Zero-Defect World || Leong
Chip Scale Review asked FormFactor CMO, Amy Leong to respond to questions that provide insights into challenges associated with automotive IC production wafer testing amid the requirement for zero-defects.

Characterization of Micro-Bumps for 3DIC Wafer Acceptance Tests | Sia
Presented at ICMTS 2019

The strong market demands to embed different functionalities from various semiconductor processing technologies into a single system continue to drive demands for 3DIC, in particular, shrinking micro-bump sizes to facilitate stacking of multiple dies. Probecards and Single DC probes are unable to address the measurement flexibilities and challenges needed for micro-bump wafer acceptance tests. In this paper, custom DC positioners with theta-X planarizing capability and true Kelvin probes have allowed for successful demonstration of consistent and repeatable test results in fully automatic micro-bump wafer acceptance tests.

Silicon Photonics: Automated wafer-level probing meets silicon photonics | Frankel, Negishi, Simmons, Rishavy, Christenson
As chip designers are pressed for ever-increasing data rates, the use of wavelength-division multiplexing (WDM) with infrared photonic signals as a data transfer medium is increasingly finding its way into CMOS silicon-based devices. Termed “silicon photonics” (SiPh), this technology is not only being used to displace traditional electrical interconnects, but also for a broad range of applications, including lidar, quantum computing, and biosensing.

New test methodologies for 5G wafer high-volume production | Bock, Damm
Companies developing 5G technologies are racing to develop the first chipsets in order to set the standard of deployment and be the leader. While initial standards for 5G were set at the end of 2017, and there are ideas about the applications of 5G, it is still unclear how exactly it will all come together. This article explores the challenges and changes in test methodology of 5G devices, and showcases the results of a collaboration with Intel.

5G Wafer Test and the New Age of Parallelism | Bock, Sia
Best Overall Presentation - SWTEST 2019

The development of new RF devices (5G and high speed digital components) is changing the landscape for RF probing. For many years, RF probing in frequencies beyond cell phone and WiFi frequencies was a niche area, only requiring a very small number of lines as well as not meeting the needs for High Volume Manufacturing (HVM).

Silicon Photonics Challenges and Solutions for Wafer Level Production Tests | FormFactor & Global Foundries
Most Inspirational Presentation - SWTEST 2019

Data centers around the world currently consume about 7% of the earth’s total power output. To satisfy the increasing demands for cloud computing and support emerging applications such as artificial intelligence, genomics revolution and data analytics, hyperscale data centers are being built around the world at an accelerated pace, with analysts predicting up to 20% of earth's total power output consumed by data centers in 2030

High Density Probe Card PCBs - Are You Your Own Worst Enemy to Achieving Higher Parallelism on your Designs? | Powell, Ojeda
Best Presentation Tutorial in Nature - SWTEST 2019

As Probe Card PCB’s complexity, and net counts increase most customers are not paying enough attention to their Power/Channel assignments to make their High Density PCB Designs possible to manufacture. Compounding this issue are tester manufacturers that create Non-optimal Channel assignment restrictions on their testers. This further complicates your ability to achieve higher parallelism testing.

Hybrid MEMS Technology 2.0 | Kister, Leong, Bhardwaj
At 2017 SWTest workshop, Qualcomm and FormFactor introduced the innovative Hybrid MEMS probe technology for advanced probing application. Hybrid MEMS technology allows multiple probe designs to be used in a single probe head design, with each probe design optimized for a specific purpose. The technical innovation to enable Hybrid design is to leverage multi-layer composite MEMS fabrication technology, which allows the optimal wafer test performance by including otherwise mutually exclusive requirements such as fine-pitch and high current carrying capability.

Improving Signal Fidelity in High Parallelism Probe Card via TTRE | Young-woo, Quay
With DRAM process node transitioning to 1X, 1Y, and 1Z, die shrinkage is driving die per wafer to the level of 2000 device or more. Wafer test using a single touchdown probe card is inevitable and can be achieved using tester resource enhancement without having to spend an excessive amount of capital expenses to upgrade existing ATEs.

Probing 5G Devices Like Its No Big Deal | Lesher, Rhodes
The rollout of 5G networks is in its infancy, but the demand for 5G devices is already here. Those devices will be in consumer products like phones, but they’ll also be integrated into new infrastructure all around us – and volumes will be hefty as a result. As with any high volume ICs, comprehensive, multi-site testing at the wafer level offers the lowest cost of test, but 5G devices have challenges not seen before in volume production. The need to support many tens of signals in the many tens of GHz range is in fact a big deal.

A Fully Automatic Electro Optical Test System Enabling the Development of a Silicon Photonics Technology Platform | FormFactor & imec
A fully automatic system for wafer-level testing of photonic devices is presented. The test system is deployed for optical process control monitor (PCM) characterization to support the ongoing development of a silicon photonics technology platform.

Tools and Techniques for Validation of VNA Calibrations with Wafer Microprobes | Kirkpatrick

Improving Probe-Tip S-parameters Measurements with Power Calibrations | Sia

Determining Probe’s Maximum Allowable Current | Cassier, Folwarski, Kister, Leong
Winner of “Most Inspirational Presentation”

Minimizing Parametric Probe Card Stray Capacitance | Soler, Levy

2014

Cost Effective 1,000V High Voltage Parametric Test Technique | Andoh, Ishibiki, Kawamata, Funatoko

Advance Low Force Probe cards Used on Solder Flip Chip Devices | Stillman, Hughes

Key Considerations to Probe Cu Pillars in High Volume Production | Wittig, Leong, Nguyen, Masi, Kister, Slessor
Winner of “Best Overall Presentation”

Can Testers and Probe Cards Keep Up With Speed Requirements for Image Sensors? | Levy, Kawamata, Hamajima

International Technology Roadmap for Semiconductors | Armstrong, Feldman, Loranger

2013

Use of Resource Sharing Techniques to Increase Parallel Test and Test Coverage in Wafer Test | Huebner

Methods of Analyzing/Predicting Scrub Margin for Pads and Bump Applications | Watson

Probing Study of Fine-pitch Cu Pillars | Leong, Wittig, Nguyen, Hulic, Slessor

Trends, Challenges, and Solutions in Advanced SoC Wafer Probe | Slessor, Kister, Eldridge, Nguyen, Leong

When Brick Wall is Not the Best, PART II (A Touch Down Optimization Study) | Wegleitner, Berry

2012

Is parametric testing about to enter a period of growth and innovation? | Levy

28nm Mobile SoC Copper Pillar Probing Study | Horas, Leong, Hulic

Crossover in TD efficiency - When Brick Wall is Not the Best | Breinlinger

Actual vs. Programmed Over Travel for Advanced Probe Cards | Berry, Breinlinger, Rincon

2011

A HOT Topic: Current Carrying Capacity, Tip Melting and Arcing | Huebner

IEEE Semiconductor Wafer Test Workshop, A Flexible Vertical MEMs Probe Card Technology for Pre-Bump and eWLP Applications | Slessor & Marshall

IEEE Semiconductor Wafer Test Workshop, Evaluation of New Probe Technology on SnAg and Copper Bumps | Wittig, Leong, Hulic

IEEE Semiconductor Wafer Test Workshop, Key Design Parameters to Maximize Probe Current Carrying Capability | Kister
Winner of "Best Paper-Tutorial in Nature"

Wafer Probes: 8 Parameters for Current-carrying Capability in Semiconductor Test | Kister

2010

Benefits of Flip Chip Wafer Sort using MEMs Multi Site Capability | Tick, Pierra

Addressing the Operating Challenges of Full Wafer Contactors | Breinlinger

Expanding Test Coverage at Sort to Reduce Overall Product Costs | Levy

High Speed Control Bus for Advanced TRE™ | Huebner
Winner - Best Presentation, Tutorial in Nature

Semicon West TechSITE North, Meeting the Economic and Technical Challenges of Wafer Test | Slessor

2009

Highest Parallel Test for DRAM Enabled through Advanced TRE (Tester Resource Enhancement) | Huebner

Improving Scrub Performance and Reducing Soak Time with a New Mechanism to Stabilize Probe Card Temperature | Harker, Lin, Pearce

MicroProbe Vx-RF Probe Card Technology | Slessor, Kister, Degan, Nagler, Nouri

IEEE Semiconductor Wafer Test Workshop, MicroProbe Vx-RF Probe Card Technology | Nagler, Degen, Nouri, Kister & Slessor

2008

MicroProbe Vx-MP Probe Card Technology | Kister, Hopkins

40k Probes on 300mm Probe Card - Another Step Towards 1 Touchdown DRAM SORT | Huebner

IEEE Semiconductor Wafer Test Workshop, MicroProbe Vx-MP Probe Card Technology | Kister & Hopkins

2007

Electrical Contact Resistance - The Key Parameter in Probe Card Performance | Kister, Hopkins
Winner - Best Data Presentation

Wafer Probing Scrub Analysis to Optimize KGD Applications | Wang, Martens, Wijeyesekera, Matsubayashi, Napier, Leong

Key Methods in Reducing Pad Crack Risk at Probing Low-k Wafers | Romreill, Leong

Probes A New Dimension in Probe Count | Huebner, Hatsumori, Pritzkau, Kawamata, Matsuo

IEEE Semiconductor Wafer Test Workshop, Electrical Contact Resistance – The Key Parameters in Probe Card Performance | Kister & Hopkins

2006

One Touch 300mm Wafer Probing | Wijeyesekera, Shinde

2005

DDR2 DRAM High-Frequency Test at Probe (HFTAP) | Ozawa, Funatoko

2004

Cost-Effective Fully Tested Die with High Frequency and High Throughput Wafer Test Solution | Ozawa, Minamihashimoto, Sagamihara

Optimization of MicroSpring® Contact Design Parameters for Low Pressure Probing | Martens, Levy