Advanced Packaging Raises the Bar for Wafer Test
As companies explore advanced packaging techniques, their search leads them to seek out cost effective testing solutions to move to high volume production.
FormFactor is the only test and measurement company that provides solutions to help customers verify device performance and yield at every stage of system integration. FormFactor helps customers lower overall manufacturing cost and enables them to gain more intelligence and knowledge at every stage of this new process; helping them to make critical decisions regarding test strategies from the lab to the fab.
Diminishing Advantages of Moore’s Law Open the Way for 3D, Heterogeneous Design Alternatives
In times gone by, the role of wafer-level test in the production of semiconductor devices was relatively straightforward. No longer. Innovative technologies have emerged that allow multiple dies to be integrated into monolithic systems that satisfy the insatiable demand for cost-effective performance in top-end applications. Data centers, artificial intelligence, autonomous vehicles and hyperrealistic graphics all demand unprecedented processing power—at a time when Moore’s Law by itself can no longer guarantee the price/performance advances seen in the past.
An innovative set of solutions to address these processing demands comes in the form of advanced packaging technologies that allow for scaling and performance gains independent of on-chip feature size. Some have already entered production, while others are under aggressive development. High Bandwith Memory (HBM) uses 3D vertical stacking of DRAM memory to drive Nividia’s graphics processing silicon to unprecedented levels. Fan Out Wafer Level Packaging (FOWLP), currently employed by Apple and TMSC, delivers both power savings and smaller footprints in portable devices. On the immediate horizon, Heterogeneous Integration (HI) technology, such as Intel’s system-in-package (SiP), allows a series of dies originating from different wafers to be integrated onto a single system substrate with extremely high interconnect density.
To be cost-effective, all of these packaging paradigms require highly optimized and accurate fabrication processes. In a multi-die system, a single defect in a single die or integration layer comes at considerable cost. As a result, wafer-level test now extends to multiple phases of the production process, making FormFactor a major participant in the development of advanced packaging technology. Our test and measurement solutions play a critical role in assuring quality and keeping manufacturing costs within bounds.
Satisfying mechanical, thermal and electrical parameters, while controlling cost
FormFactor is thoroughly acquainted with these challenges, which apply not only to HBM, but to a diversity of advanced packaging solutions, such as Intel’s Foveros and TSMC’s Integrated Fanout, as well as others. Through our ongoing collaborations with IC manufacturers and ATE providers, we’ve moved forward with solutions that keep pace with the rapid progress in advanced packaging. For example, we deploy composite metal MEMS probes, sometimes mix-and-match Hybrid MEMS design, in probe cards to deliver finely tuned pitch, high current carrying capacity, and reduced power impedance.
At the same time, we fully realize the need to provide solutions that remain economically feasible in a rapidly changing manufacture/test context. One good example is the role of known good die (KGD) in advanced packaging. It makes sense to test each subcomponent to the point of KGD, but when individual components enter the integration phase, the situation becomes more complex. Take the case of HBM: As each layer of DRAM is added to the stack, to fully test the entire stack each time a new layer is added is a relatively expensive process. The cost of rejection rises as the number of layers increases. At some point, the cost of test outweighs the value added when the system is completed.
At FormFactor, we offer smart test options to achieve the optimal balance between the test cost and test content. For full test coverage KGD test flow, our Altius™ probe card supports 45μm grid-array pitch microbump pitch testing and >3Gb/s at-speed verification. For more mature test flow with acceptable risk for limited test, we also offer the industry’s highest throughput probe card, the SmartMatrix™ product, to dramatically reduce test cost per die. Manufactured by AI-based MEMS probe assembly, SmartMatrix™ allows testing the entire 300mm wafer simultaneously.