New Line of Wafer Probe Cards Helps Lower the Cost of Test of Wire Bond Logic and System-on-Chip Devices
October 23, 2007
TrueScaleTM products fulfill growing need in wire bond logic market for multi-site testing
LIVERMORE, Calif. – October 23, 2007 – FormFactor, Inc. (Nasdaq: FORM) today announced a new family of advanced wafer probe cards designed to address the rising cost and technology challenges associated with testing wire bond logic and system-on-chip (SoC) devices. The TrueScaleTM product family leverages FormFactor’s MicroSpring® contact technology to provide increased throughput and uptime that wire bond logic and SoC manufacturers need to lower their test cost per die and support their technology roadmaps for tighter pad pitches.
Limitations with conventional cantilever probing solutions allow for only a few devices to be tested in parallel today. At higher levels of parallelism, these probing solutions require frequent maintenance—in many cases after only a few touchdowns—to ensure the contacts are aligned properly with the test pads on the wafer. In contrast, FormFactor’s TrueScale probe cards leverage the company’s proprietary MicroSpring contact design to allow robust contact performance, significantly higher pin counts, and fewer touchdowns per wafer than alternative technologies—increasing test throughput and enabling greater test cost reductions.
FormFactor’s cards feature the ability to reduce device pad pitch, with a roadmap to scale to 30- micron pitch inline. The high precision of the MicroSpring contacts, enabled by the semiconductor-like manufacturing processes used to produce them, minimizes pad damage and allows for greater test uptime. In addition, the improved electrical performance of the TrueScale probe card family allows customers to fully test the performance limits of their devices at probe—ensuring confidence that devices meet performance specifications before they are packaged.
According to market research firm, TechSearch International, approximately 90 percent of all ICs currently shipped are wire bonded. Wire bond logic and SoC devices are utilized in a wide variety of applications—from wireless baseband and digital media, such as mobile phones and MP3 players, to automotive microcontrollers and smart cards. As more logic devices are integrated into system-in-package (SiP) and other multi-chip package solutions for consumer applications, the need for fully tested die at the wafer-level grows.
“Many of the same test efficiency and cost-of-ownership issues that drove customer selection of our technology in memory test markets are now becoming more critical for high-volume logic and SoC device testing,” stated Stefan Zschiegner, vice president and general manager of FormFactor’s SoC Product Business Group. “An incremental increase in test parallelism can result in millions of dollars in savings to our customers. Our logic and SoC probe card solutions continue to drive these efficiencies.”
FormFactor is now taking orders for the TrueScale wafer probe card family.
Statements in this press release that are not strictly historical in nature are forward-looking statements within the meaning of the federal securities laws, including statements regarding business momentum, demand for our products and solutions and future growth. These forward- looking statements are based on current information and expectations that are inherently subject to change and involve a number of risks and uncertainties. Actual events or results might differ materially from those in any forward-looking statement due to various factors, including, but not limited to: the ability of the company to introduce products that increase throughput and uptime for wire bond logic and SoC manufacturers to lower their test costs per die and to support their technology roadmaps through tighter pad pitches; the ability of the company’s MicroSpring contact design to enable robust contact performance, significantly higher pin counts, and fewer touchdowns per wafer than alternative technologies; the company’s ability to deliver products that allow customers to fully test the performance limits of their devices at probe; and IC manufacturers selection of increased parallelism to test logic and SoC devices. Additional information concerning factors that could cause actual events or results to differ materially and adversely from those in any forward-looking statement is contained in the company’s filings with the Securities and Exchange Commission, including the company’s Form 10-K for the fiscal period ended December 30, 2006 and subsequent Form 10- Q and 8-K filings. Copies of the company’s SEC filings are available at http://investors.formfactor.com/edgar.cfm. The company assumes no obligation to update the information in this press release, to revise any forward-looking statements or to update the reasons actual results could differ materially and adversely from those anticipated in forward- looking statements.