As semiconductor suppliers strive to increase their throughput and lower their test costs, probe card parallelism continues to increase. State of the art probe card designs require up to 80,000 probes and the industry is driving for as much as 150,000 probes in the future. Where are the limitations? Total probe force will be >200 kgf and while there are testers that can handle this amount of force, probe card deflection needs to be considered to maintain high volume production requirements.
Today, the ratio of actual overtravel on the probes to the programmed overtravel can be as low as 30% which makes achieving low contact resistance between probe tip and wafer a challenge. Increasing probe card stiffness is simple in theory but the space constraints between probe card and tester plus the need to populate the PCB with many components makes this very difficult to achieve. In addition to the tester, the prober and probe card metrology tools will need to accommodate this higher force as well.
This webinar will provide a survey of the test equipment industry and identify the chief limitations including where probe card mechanical design needs to improve.