The semiconductor industry continues to see the relentless downscaling of gate length and development of new architectures for silicon-based transistor to 2 nm and beyond. The on-state currents of such advanced transistors are increasing with decreasing supply voltages. Their off-state currents are kept very low to reduce power consumption. Smaller test pads to reduce lithography costs and the use of copper backend metallization have increased the difficulties for probes to have low and stable contact resistance as there are little fresh pad metal available for deeper probe scrubs or re-probing. These issues aggravate especially at elevated temperatures when the pad aluminum cap layers have been probed and their underlying copper metallization oxidize rapidly, hindering the ability to achieve good probe contacts. In this talk, we introduce the next generation advanced guarded DC probes with small probe scrubs, low leakage performance and true Kelvin force sense probe tips to address the test challenges of making precise and consistent device modelling wafer measurements.