With mobile devices getting ever-thinner, the race continues to reduce chip package profiles, while simultaneously increasing feature integration and adding new functionality – all without driving up power consumption.
This means dramatic changes for IC design and production. Achieving the critical 3D shrinks depends on cutting-edge 28nm, 20nm and 14/16nm wafer process technology, as well as “More-than-Moore” advanced packaging technologies, like Cu pillars and 2.5D/3D probing.
Such changes present big wafer test challenges for SoCs and memory ICs. Take low-power DRAM devices (LPDDR2 and LPDDR3) for example. Here, the mandate is to reduce mobile memory power even as memory arrays grow larger. That’s where high-frequency test-at-probe (HFTAP) can be a big success driver. FormFactor leads this effort with new technology that enables mobile DRAM wafer test speeds of up to 2.4Gb/s – the highest specification testing possible for LPDDR2 and LPDDR3 devices – and an unprecedented enabler of full Known Good Die test capability.