As semiconductor devices become more complex, wafer test is evolving just as quickly. AI infrastructure, high-performance computing (HPC), advanced packaging, and next-generation memory architectures are pushing test requirements further than ever before.

From higher data rates to tighter geometries and broader thermal operating ranges, today’s wafer-level test environments must balance precision, throughput, and efficiency at every stage of development and production.

At SWTest 2026, taking place June 8–10 in Carlsbad, California, FormFactor will participate in several technical sessions focused on these emerging challenges. The company’s contributions span advanced memory testing, high-frequency measurement, micro-bump probing, and test cell optimization, areas that continue to shape the future of semiconductor validation and manufacturing.

These sessions also highlight many of the same trends shaping wafer test across the semiconductor industry today.


Addressing Advanced Packaging and HBM Test Challenges

Advanced packaging technologies such as 2.5D and 3D integration are transforming semiconductor design. At the same time, high-bandwidth memory (HBM) is becoming essential for AI accelerators and data center architectures. Together, these technologies are creating new demands on wafer-level test and probe card performance.

One of FormFactor’s featured SWTest presentations focuses specifically on multi-temperature HBM testing:

A Novel Advanced Probe Card Approach for Multi-Temperature HBM Testing

Monday, June 8 | 4:30 – 5:00 PM
Session: System-Level Integration and HBM Specific Solutions

Featuring Timothy Blomgren, Kalyanjit Ghosh, and BeomKu Lee (FormFactor), in collaboration with SK hynix.

This session looks at probe card approaches that help support HBM testing across a wide range of temperatures. As HBM devices are pushed into more demanding applications, engineers need to validate performance and reliability across a broad range of operating conditions while maintaining signal integrity and contact stability throughout the test process.

FormFactor will also contribute to discussions around micro-bump probing and advanced packaging scalability:

Micro Bump Probing: High Volume Experience Driven Capability Demonstration and Direction for Advanced 3D/2.5D Packaging

Wednesday, June 10 | 8:00 – 8:30 AM
Session: Challenges of Wafer Test Scaling

Presented by Jeremy Streifer and Ethan Caughey (FormFactor), in collaboration with Intel Foundry.

This presentation shares practical lessons from high-volume micro-bump probing applications, including the scaling challenges associated with increasingly fine-pitch interconnects.

As advanced packaging designs become more complex, wafer probing technologies need to keep pace, delivering the accuracy, reliability, and durability required for next-generation semiconductor devices.


Pushing High-Frequency Measurement Capabilities

Data rates continue climbing across networking, AI, and HPC applications, increasing the need for higher-frequency wafer-level characterization.

To support these next-generation devices, FormFactor will present work related to probe card measurement capability at frequencies up to 120 GHz:

First Probe Card for DUT Measurements at 120 GHz to Support 1.6 Tbps

Poster Session | Monday, June 8 and Tuesday, June 9

Presented by Christopher Lemoine (FormFactor).

This work introduces a probe card architecture capable of supporting DUT measurements up to 120 GHz, helping enable characterization for technologies associated with emerging 1.6 Tbps applications.

As frequencies climb higher, maintaining accurate wafer-level measurements becomes much more challenging due to signal loss, parasitics, and calibration complexity. Advancements in probe card design and RF measurement capability are becoming increasingly important for supporting future high-speed semiconductor development.


Improving Test Cell Efficiency and Maintenance

Beyond measurement performance, semiconductor manufacturers are also focused on improving operational efficiency, minimizing downtime, and reducing overall cost of ownership.

FormFactor will participate in a collaborative session addressing these challenges:

The Dual-Action MEMS Solution: Cleaning Innovation Meets Cost Reduction

Tuesday, June 9 | 2:30 – 3:00 PM
Session: Test Cell Optimization

Featuring contributors from Texas Instruments, Entegris, and FormFactor.

This presentation explores a MEMS-based probe card cleaning approach aimed at reducing contamination and improving maintenance efficiency in wafer test environments.

Even small improvements in cleaning processes and uptime can have a meaningful impact on production throughput, equipment utilization, and long-term operating costs, especially in high-volume manufacturing environments.


Common Themes Across SWTest 2026

Although the presentations cover different technologies and applications, several broader trends connect the work being shared at SWTest 2026:

  • Increasing complexity in advanced packaging and HBM testing
  • Growing demand for high-frequency wafer-level measurement capability
  • Continued focus on improving test cell efficiency and uptime
  • Greater emphasis on scalable, production-ready wafer test methodologies

These trends show just how quickly semiconductor architectures are changing, and how important wafer-level test has become in keeping development and production moving forward.

Looking Ahead

SWTest continues to bring together engineers, researchers, and semiconductor leaders focused on solving some of the industry’s most pressing wafer test challenges.

FormFactor’s participation at SWTest 2026 highlights the company’s continued collaboration with customers and industry partners to advance wafer probing, measurement, and test cell technologies that support next-generation semiconductor innovation.

As AI, HPC, advanced memory, and advanced packaging continue pushing performance forward, wafer test will remain a critical part of enabling the next generation of semiconductor innovation.

Hope to see you in Carlsbad!