Three Requirements of Successful Electromigration Wafer-Level Testing
December 21, 2017
Wafer level testing of intrinsic Electromigration offers excellent advantages over traditional package level EM test in terms of faster results and better data integrity, and has been shown to be a valid and useful complementary test method.
Why is there a shift from package-level reliability (PLR) testing to wafer-level reliability (WLR) testing? Quite simply, there’s a demand for faster results and better data integrity, and these needs also apply to electromigration test (EM). The difference is that with EM, there are long test times, higher temperatures, and large sample sizes. In the past, this often meant that PLR was less expensive than WLR, but not so anymore!
EM WLR testing can now deliver the reliability testing requirements the industry needs, including:
- Faster Results. Increasing stakes in the technology race apply pressure on reliability labs for quicker answers, and the rising interconnect complexity of new nodes demands investigation of more materials and structure types than ever before. This impels the industry to pursue methods of accelerating design and qualification cycles, and utilizing EM WLR to complement EM PLR tangibly enables reliability departments to respond to this challenge.
Packaging devices under test (DUTs) for PLR involves sending the wafer to an in-house or external packaging facility to saw and bond the test structures into ceramic DIPs. WLR entirely bypasses this packaging step to test the wafer directly. This simplifies test program logistics and eliminates expenses for dicing/bonding services, sacrificial packages, and shipping. Most importantly, this expedites the test results by days or even weeks.
The improved response times provided by EM WLR are especially valuable during new process development, fab line qualification efforts, adding customer-specific recipes to foundry lines, responding to process excursions identified by other SPC methods, and whenever process tuning is frequent or urgent.
- Better Data Integrity. Reliability margins have shrunk dramatically with recent nodes, rendering simple “worst-case” and one-size-fits-all analysis moot. To massage maximum performance out of each IC element, design rules have become progressively more sophisticated; this demands a broader range of test conditions to check all corner cases and applications, and ever more accurate data for every case tested.
Data integrity is therefore essential, but DUT packaging comes with multiple damage threats. Sawing the wafer to singulate the test structures uses water, which can be absorbed by the low-k or ultra low-k dielectric. There are also opportunities for electrostatic discharge (ESD) damage to DUTs, which occurs during package bonding, shipping, handling, and loading the package into the system for test. Water and ESD damage is sometimes immediately apparent (hard-failing DUTs are easily screened out prior to test), but sometimes these can be latent effects, which emerge only later during test to skew results unpredictably. These issues are especially problematic for technology development when guard rings for protection may not be present, but can negatively impact reliability evaluation of mature processes as well.
EM WLR provides the safest approach to test, without EM PLR’s risk of potential data corruption due to moisture absorption and ESD during bonding, shipping, handling, and loading.
- Legitimacy. Decades of industry interconnect testing have yielded an enormous library of baseline reference data and trust in the EM PLR method. EM WLR is therefore only useful if it follows the same intrinsic test methods and generates data, which can be similarly trusted, such that the data may be analyzed coincident with EM PLR data.
Fortunately, when using proper equipment and applying traditional intrinsic electromigration test methods (e.g., constant current stress rather than “fast” WLR methods such as SWEAT or isothermal), EM WLR generates lognormal distributions, which correlate very well to EM PLR, indicating similar electrical and thermal accelerations for the two methods. These lognormal plots show the progression of DUT failures over time under stress and feed directly into the Black’s Equation analytics used for intrinsic lifetime prediction.
The data sets were treated with the Wilcoxon Group Homogeneity test (see below), which confirmed that the differences between EM PLR and EM WLR results were statistically indistinguishable.
The net result of this correlation is that EM PLR and EM WLR data can indeed be used interchangeably and blended for analysis. Reliability test labs may therefore select the optimum mix of WLR and PLR capabilities to best meet their demands, processes, and budgets.
Wafer level testing of intrinsic Electromigration offers excellent advantages over traditional package level EM test in terms of faster results and better data integrity, and has been shown to be a valid and useful complementary test method. Our innovative, integrated, validated Estrada-EM solution is the first to truly meet the demands of EM WLR, and further offers a number of unique performance capabilities to produce the best available EM WLR test experience and results.