FormFactor Presentations Preview: SWTest 2021
August 12, 2021
FormFactor will be delivering several presentations at the SWTest 2021 Conference, August 30 – September 1, in San Diego, California. SWTest 2021 will also be ON-DEMAND Access 24/7 from September 2 – October 2, 2021. Here’s a rundown of what will be presented.
FormFactor will be delivering several presentations at the SWTest 2021 Conference, August 30 – September 1, in San Diego, California. SWTest 2021 will also be ON-DEMAND Access 24/7 from September 2 – October 2, 2021. Here’s a rundown of what will be presented:
August 30, 10:30 – 11:00: Daniel Bock, PhD and David Raschko – The Digital Revolution: NRZ to PAM4
With increasing demand to process more data and pass large amounts of data through servers, cellular devices, and even within the computer for the highest performing video cards, the need for more complex digital processing is becoming greater than ever. This becomes evident in the next generation PCIe requirements with the move from PCIe 5 to PCIe 6. The current specifications are to double the total throughput per pipeline for a dramatic increase in the total performance. Traditionally, non-return-to-zero (NRZ) has been the standard for digital encoding; however, this quickly runs out of steam after 40 Gbps where the loss in the system becomes too great to manage and closes the eye. Pulse Amplitude Modulation 4-Level (PAM4) allows the same fundamental frequency to be used as NRZ while effectively doubling the baud rate by introducing two additional amplitude levels to the traditional 2 level encoding.
The impacts of this at wafer test are profound and are still in the early stages of being defined. The easily identified issues are the reduction in signal-to-noise ratio, higher sensitivity to return loss and impedance matching, and increased impact of jitter on the system resulting in higher performance test cells. We will show some of the impacts of NRZ compared to PAM4 on wafer test through example probe cards and describe the changing test requirements.
In addition to this we will also go over the frequency and digital divide in test and how the fundamental test vectors are derived and present relationships between the two. The implications of this are higher bandwidth probe card capabilities and a divergence in the test vectors that are dependent on the measurement method being used, including S-Parameter measurements, eye diagrams, loopback testing, and Bit Error Rate Test (BERT) to name just a few examples.
September 1, 8:00 – 8:30: Cameron Harker, Yohannes Desta, and Pouya Dastmalchi – Challenges of Expanding Large Area Active Array for Fine Pitch Vertical Probe Cards
Semiconductor manufacturers are on a relentless drive to reduce the total cost of test at sort. A major contributor to reducing cost of test is increasing simulations Device Under Test which requires a subsequent increase in the probe card active area. For wire bond applications, increasing the active area must also meet the requirements of an extremely wide temperature range, very fine pitch and electrical performance. These factors. Along with other considerations, increases the probe card design complexity exponentially.
Vertical probe card solutions must evolve to meet these new testing challenges both at architectural and probe level. Probe card architectures need to be managed for mechanical stresses and CTE match between substrate and guide plates, support electrical performance requirements to meet device test requirements and achieve increased spring count requirements.
FormFactor has developed a new probe card architecture that meets these challenges. The recently qualified 60um pitch probe card architecture has been developed to address the challenges of fine pitch, high CCC, high temperature range for wire bond probing applications. Additionally, the new architecture incorporates the benefits of an optimized 60um capable MEMS vertical spring, optimal material selection and automated manufacturing processes which provides superior lifetime, stable CRES and tighter pin-pad alignment.
September 1, 10:00 – 10:30: Alan Liao – Next Generation KGD Memory Test Achieved Wafer Level Speed Beyond 3GHz/6Gbps
Recent industry wide adoption of heterogeneous integrated system enabled by 2.5D and 3D advanced packaging technology is driving up the demand for known-good-die. Coupled with the advancement on DRAM and High Bandwidth Memory (HBM) native speed capability, the latest memory is running beyond 2GHz (4Gbps) which is pushing the limit on existing ATE testers. Recent joint effort between SK Hynix, FormFactor, and Advantest successfully demonstrated that beyond 3GHz is achievable. This session discusses the design challenges overcame in this collaboration from a system level signal integrity and power delivery perspective.
September 1, 10:30 – 11:00: Joe Ceremuga and Cameron Harker – Next Generation SmartMatrix Probe Card Technology Enables 3000-Parallelism 1TD Test for 1Z DRAM Process Node
The DRAM technology process node continues to shrink, driven by the demand to increase bit density and reduce memory device cost. With the recent accelerated transition from the 1Y to 1Z process node, die count per wafer is increasing rapidly. Wafer sort throughput must advance to achieve the target cost without adding significant capital expenditure to the existing test floor. Samsung and Formfactor have been working together, and successfully developed and qualified the next generation DRAM probe card that leverages FormFactor’s ATRE technology for 3000-parallelism and beyond. FormFactor’s SmartMatrix 3000XP probe card enables remarkable high-parallelism test throughput by extending ATE tester resource sharing up to X32. This session discusses the key technology enablers of the SmartMatrix 3000XP product architecture, and the design challenges overcame during this successful collaboration.
Hope to see you there!