The Test Vision Symposium is a premier workshop for semiconductor and system test experts, organized annually in association with Semicon West to discuss coming trends, innovations, and requirements for semiconductor test. Our team had two great presentations worth sharing.
Probe Card Challenges for Expanding Arrays of Fine Pad Pitch Devices to Test Under Wide Temperature Range
Semiconductor manufacturers are on a relentless drive to reduce the total cost of test at sort. A major contributor to reducing cost of test is increasing simulations Device Under Test which requires a subsequent increase in the probe card active area. For wire bond applications, increasing the active area must also meet the requirements of an extremely wide temperature range, very fine pitch and electrical performance. These factors. Along with other considerations, increases the probe card design complexity exponentially.
Vertical probe card solutions must evolve to meet these new testing challenges both at architectural and probe level. Probe card architectures need to be managed for mechanical stresses and CTE match between substrate and guide plates, support electrical performance requirements to meet device test requirements and achieve increased spring count requirements.
FormFactor has developed a new probe card architecture that meets these challenges. The recently qualified 60um pitch probe card architecture has been developed to address the challenges of fine pitch, high CCC, high temperature range for wire bond probing applications. Additionally, the new architecture incorporates the benefits of an optimized 60um capable MEMS vertical spring, optimal material selection and automated manufacturing processes which provides superior lifetime, stable CRES and tighter pin-pad alignment.
5G MmWave: Multi-site RF Probe Cards Enable Lower Cost-of-test in Mass Production
5G mmWave systems are here. Advanced Antenna-in-Package modules and RFFE chipsets are integral to the latest generation of high-end smartphones and tablets, and this capability is becoming more ubiquitous in 2022. These chips, containing a massive amount of mmW content, are ramping in mass production, and the companies producing them need a way to reduce cost of RF test. Our collective challenge spans multiple organizations requiring concerted coordination between sub-systems and immaculate preservation of impedance. Additionally, direct measurement test time is appreciable for advanced-RF devices, which drives the need for more parallel measurement insertions.
One converging approach, is the use of RF switching on PCB to expand available tester channels and support multi-site probe heads through sequential-parallel testing. To realize actual cost reduction, tester and probe card companies need to evolve quickly to support increased parallelism of mmWave testing.
This session drills down into the RF test cell to examine enhancements enabling increased parallelism using new probe head architectures. The development efforts began by enlarging the active probing area using an advanced membrane process. This new capability created a canvas for RF engineers to develop a host of transmission line structures aimed at high density RF routing from the die to the PCB. Innovation continued – with several loopback options, and a host of new structures to support densification. Another problem uniquely solved with the new membrane, is the ability to support 50 Ohm and non-50 Ohm transmission lines simultaneously to match the impedance needs of the tester and overall performance expectations.
We’ll share examples and typical S-parameter performance for several line types during this session. In closing, this collection of new probe head elements is enabling test engineers to configure their high-volume RF test solutions in novel ways, and we are eager to equip the industry with new test possibilities.