COMPASS 2023, FormFactor’s test and measurement community event, is a wrap, but you can still enjoy all the FormFactor presentations that are now available for on-demand viewing.

Pyramid Probe: RF Calibration and Probe Aging Considerations in HVM High Speed IO Devices – Pratik Ghate, Principal RF Engineer

The proliferation of AI, exemplified by technologies like ChatGPT and BING AI, necessitates substantial investments in the expansion of data centers, propelling increased data rates in IO devices. To achieve these elevated data rates, wafer testing is transitioning to bandwidths exceeding 60 GHz. Pyramid Probes, extensively employed for wafer testing at frequencies up to 81 GHz and in high-volume manufacturing (HVM), utilize micro-strip or coplanar waveguide (CPW) transmission lines to ensure controlled impedance and low loss (less than 6 dB at 67 GHz), delivering industry-leading performance during wafer testing.

However, in the conventional layout, the signal trace is oriented towards the wafer, with a mere 70 micrometers of separation, making it susceptible to occasional coupling with structures on the wafer. This coupling can have noteworthy implications in terms of Device Under Test (DUT) performance and Radio Frequency (RF) calibration of the probe head. Additionally, as the probe ages and the tips shorten, bringing the microstrip closer to the wafer, one can anticipate an increase in this coupling.

To mitigate this coupling, Pyramid Probes employing an inverted microstrip configuration, with the ground positioned between the transmission line and the wafer, are now available. This study aims to utilize probes with both standard and inverted microstrips to assess the performance of Transimpedance Amplifiers (TIAs). Comparative analyses of measurements taken before and after aging the probes will be conducted to characterize these effects. Furthermore, various calibration methods (Short-Open-Load-Reciprocal (SOLR), Short-Open-Load-Thru (SOLT), and Short-Open-Load de-embed (SOL de-embed)) will be explored and compared to offer recommendations for calibration procedures.

How FormFactor’s Known Good Die Test Enables Advanced Packaging for High Bandwidth Memory – Solutions and Latest Trends – David Cooke, Product Marketing Manager

The demand for high-bandwidth computing has spurred the advancement of 3D Heterogeneous modules. These vertically stacked memory packages designed for High Bandwidth Memory offer numerous advantages over traditional modules, including lower power consumption, significantly increased memory storage, enhanced performance, and a progressively smaller footprint.

The revenues from Advanced Packaging Integrated Circuits (ICs) continue to experience year-on-year growth. The introduction of this technology has underscored the importance of conducting known good die tests on Through-Silicon Via (TSV)-connected memory stacks to mitigate risks and reduce costs. Early testing data on stack yield post-manufacturing is crucial for controlling final expenses. FormFactor’s probe solutions serve as the essential testing medium for aluminum pads, enabling sort and functional speed tests through FFI’s T11 probe family, as well as for copper bumps with vertical Microelectromechanical Systems (MEMs) in the MF family.

Pharos Vertical and Edge Coupling Low Loss SiPh Wafer Test with Fully Automated Calibration – From Probe Install to Successful V-groove Wafer Level Test in 90 Minutes – Simon Reissmann, Sr. Principal Applications Engineer

In this presentation, we will explore FormFactor’s cutting-edge silicon photonics coupling technology, Pharos, renowned for its efficacy in edge coupling within V grooves and achieving minimal loss coupling on grating couplers. Additionally, we will delve into the latest advancements in the silicon photonics software solution suite, featuring a newly introduced automated calibration routine that can be executed with just four mouse clicks.

FormFactor’s Silicon Photonics (SiPh) solution incorporates a built-in power measuring function, enabling the quantification of laser output directly from one of the Pharos fiber channels. This functionality provides users with the flexibility to seamlessly transition from on-wafer measurements to an auxiliary site, verify laser power from the probes, automatically position one of the eight channels, and return to the last measured die or subdie, all through a single integrated command. This eliminates the need for manual navigation, probe positioning, and mitigates user errors, resulting in a significant time-saving advantage.

Moreover, the four-mouse-click automated calibration ensures the eradication of manual errors. This streamlined routine guarantees consistent and repeatable calibration results without oversight, offering significant time savings in the process.

Measuring Superconducting Material Properties for Cryogenic Chip Development – Brandon Boiko, Sr. Applications Engineer

Numerous advancements in the Quantum and High-Performance Computing sectors hinge on the application of superconducting materials and their distinctive attributes. Key components such as Superconducting Nanowire Single-Photon Detectors (SNSPDs) and Superconducting Quantum Interference Devices (SQUIDs) commonly utilize superconductors like Nb and Al, chosen for their favorable transition temperatures of approximately 10K and 1K, respectively. The continuous exploration of novel superconductors with enhanced performance and manufacturability remains an active area of research. This presentation will delve into the fundamental measurement methodologies and recommended practices for characterizing the transition temperature of superconducting materials.

Maximizing CCC in a Probe Card and the March to an Unburnable Probe – Hadi Najar, Sr. Principal Engineer Mechanical Design

Data centers and High-Performance-Compute (HPC) applications are rapidly approaching, and in some cases, surpassing 1kW of total power on a single chip under normal operating conditions. The shift to new nodes, alongside the emergence of novel applications, further amplifies the total power per unit area in semiconductors. This exacerbates the challenge of handling increased power and thermal output during testing, even in low-power consumption applications like mobile application processors.

The ongoing escalation in device output power introduces multiple hurdles in wafer testing, particularly in preserving contactor integrity in high-current and high-temperature environments. To counter this trend, advancements in the Current Carrying Capacity (CCC) of the probe during testing must progress at a rate commensurate with the observed increase in power in the Device Under Test (DUT). This ensures enhanced uptimes and a reduced cost of test.

This paper will explore various techniques deployed in the probe card to optimize CCC, aiming to achieve an effective CCC exceeding 2.5A in a probe card with an 80um minimum pitch. The discussion will encompass both innovative probe developments and architectural enhancements designed to maintain probe integrity in high-stress, high-current environments.

Achieving Traceable RFCMOS Ft and Fmax Wafer Measurements – Pranav Shrivastava, Principal Applications Engineer

Ft and Fmax serve as crucial benchmarks for RFCMOS transistors, posing a significant industry challenge to reliably characterize and measure Fmax. The precision, repeatability, and traceability of wafer-level Ft and Fmax measurements are paramount for circuit designers as they embark on RFIC design endeavors. These measurements are essential to support the evolving landscape of high data rate, low latency wireless applications, including beyond 5G, wireless multimedia, IoT, big data, and vehicular positioning systems.

The study presented here delves into the impact of RF probe contact resistance on the test pads of calibration standards and devices, specifically how it influences the Ft and Fmax measurements of RFCMOS transistors. The research reveals that suboptimal probe contact on calibration standards results in a substantial extracted load standard inductance when utilizing eLRRM calibration, thereby diminishing the transistor’s Fmax. This presentation introduces a novel RF wafer test strategy designed to assist device and test engineers in attaining precise, repeatable, and traceable Ft and Fmax measurements.

Simplifying Photonic Test and Measurement at Cryogenic Temperatures – Jack De Grave, Director of Business Development

Emerging quantum technologies, encompassing quantum communications, sensing, and computing, hold the potential to transform digital security, finance, logistics, pharmaceuticals, and various other sectors in the coming decades. Progressing these quantum technologies necessitates innovative test and measurement strategies capable of reliably testing superconducting and integrated photonic devices below their transition temperatures, typically less than 4K.

This presentation will delve into FormFactor’s photonics application layer, featuring an automated fiber array scan and alignment function designed to streamline testing in cryogenic conditions. This technology is integrated with a new cooling system, enabling automated test and measurement in a sub-2K environment. We will showcase the photonic application layer on our latest solution, the IQ2000 rapid chip-scale tester, and present early results.

Next Generation DC Probes for Accurate and Repeatable Device Modeling Measurements – Dr. Choon Beng Sia, Test Technologist

The semiconductor industry is experiencing an unrelenting trend towards reducing gate length and developing new architectures for silicon-based transistors, pushing towards 2 nm and beyond. Advanced transistors at these scales exhibit increasing on-state currents alongside decreasing supply voltages, with a concerted effort to keep off-state currents extremely low for minimized power consumption. Challenges arise from smaller test pads, aimed at reducing lithography costs, and the adoption of copper backend metallization. These factors amplify difficulties for probes to maintain low and stable contact resistance, given the limited fresh pad metal available for deeper probe scrubs or re-probing.

These challenges become particularly pronounced at elevated temperatures, where probing the pad aluminum cap layers leads to rapid oxidation of the underlying copper metallization, hindering the establishment of reliable probe contacts. This presentation introduces the next generation of advanced guarded DC probes, designed with small probe scrubs, low leakage performance, and true Kelvin force sense probe tips. These innovations address the testing challenges associated with achieving precise and consistent device modeling wafer measurements.

To view these presentations, visit the COMPASS website. We’ll see you at the next COMPASS!