FormFactor recently participated in the SWTest Asia Conference – November 2-3, 2023 – and wanted to share a couple of presentations that were given by Pratik Ghate and Dr. Hadi Najar.

Complex Impedance Matching Structures for Advanced On–Wafer AiP Testing | Pratik Ghate

The growing demand for more integrated and miniaturized solutions in modern wireless communication systems is driven by the increasing frequency of operation and operational bandwidths. One significant development in this direction is the integration of antennas directly onto the chip or within the package of the wireless device. This concept is known as “antenna-on-chip” (AoC) or “antenna-in-package” (AiP). The integration of antennas (either AoC or AiP) in the package provides numerous advantages, including the reduction of parasitic effects, improved electromagnetic performance, improved efficiency, miniaturization of the system, simplified design, etc. In this work, we present complex impedance matching structures embedded in FormFactor’s Pyramid Core that will play a major role in improving wafer test coverage with better yield and lower cost of ownership (COO) as immediate benefits.

Current Carrying Capacity Maximization in Probe Cards and the Path to An Unburnable Probe | Dr. Hadi Najar

Data centers and High-Performance-Compute (HPC) applications are quickly approaching, and even exceeding, 1 kW of total power in a single chip under normal operating conditions. In addition to new applications, the transition to new nodes further increases the total power per unit area in a semiconductor, which compounds the challenge of increased power and thermal output of a device during testing, even in low-power consumption applications such as mobile application processors. This continuous increase in device output power creates several challenges regarding wafer testing, particularly in maintaining contactor integrity at high current and in high-temperature environments. To address this trend, higher CCC in the probe during testing must advance at a rate similar to the increased power observed in the DUT, leading to increased uptimes and lower cost of testing. This paper will discuss several techniques that can be utilized in the probe card to maximize CCC and achieve an effective CCC of >2.5 A in a probe card at an 80um minimum pitch. These techniques include both new probe developments and architectural improvements to maintain probe integrity in a high-stress, high-current environment.

Here are some photos from the conference: