FormFactor is proud to be an exhibitor at SWTest 2025, the premier industry conference dedicated exclusively to semiconductor wafer and die-level probe testing.

We invite you to stop by Booth 403 in the exhibition hall at the Omni La Costa Resort in Carlsbad, CA, from June 2–4, 2025, to explore our latest innovations and speak with our experts. Whether you’re looking to enhance probe performance, improve yield, or refine your test strategies, we’re here to help.

In addition to showcasing our solutions on the exhibit floor, FormFactor is presenting a series of technical sessions that delve into the latest advancements in semiconductor testing. These presentations will cover a range of topics, including MEMS probe technology, RF calibration, and silicon photonics, providing valuable insights into the evolving landscape of wafer and die-level testing.

We encourage you to attend these sessions to gain a deeper understanding of the challenges and innovations shaping the industry. Here’s a look at our presentation schedule:

Technical Presentations:

MEMS Probe Card Solution to Address Parametric Test Challenges

Presenter: Mukesh Selvaraj, VP, Product Development, FormFactor

Date: Monday, June 2
Time: 2:30 p.m. – 3:00 p.m.

Parametric testing plays a key role in semiconductor manufacturing by providing critical data essential for lowering costs, improving quality, and achieving higher yields. Parametric probe cards are widely used for in-line and end-of-line testing to verify quality, reliability, process monitoring, and process optimization, and to perform performance checks. This allows for early defect detection and yield improvement.

This presentation provides an overview of current and future test challenges for parametric testing. It includes MEMS probe card development details and shares in-line and end-of-line test results from FormFactor and Intel. It will also cover high-precision interchangeable MEMS probing solutions, with test results for small test pads, fine pitch, high density, narrow scribe lines, long lifetime, low leakage, contact resistance, very low scrub ratio, and various pad materials.

 

Innovative Testing Strategies for Silicon Photonic Devices in Engineering and Production Applications

Presenters:

  • Dan Rishavy, Strategic Market Development Director
  • Quan Yuan, Sr. Staff Systems Design Engineer

Date: Monday, June 2
Time: 5:00 p.m.

Abstract Coming Soon.

A Novel Approach for Increased Probe Card Parallelism Utilizing Device Package Substrates

Presenters:

  • Cameron Harker, Sr. Director, Business Development
  • Leon Besprozvanny, Sr. Principal Manufacturing Engineer

Date: Tuesday, June 3
Time: 8:30 a.m. – 9:00 a.m.

In the semiconductor industry, the relentless pursuit of higher feature counts, transistor densities, and device package complexity has led to increased demands for innovative testing solutions. To meet these demands, the industry is exploring ways to reduce test costs by achieving increased probe card parallelism.

We introduce an innovative probe card solution that enhances parallelism by leveraging existing device package substrates. These substrates serve as space transformers for the probe card, providing the interface between the probe head and the probe card PCB. This approach streamlines the probe card design cycle by eliminating the need to design custom multilayer organic (MLO) space transformers, reducing design complexity, cost, and lead times. Additionally, it supports cost reduction by enabling the integration of Design for Test (DFT) considerations early in the device package and design layout, allowing customers to further enhance manufacturability and long-term test cost efficiency. This solution also provides a more one-to-one match for signal integrity (SI) and power integrity (PI) conditions, aligning probe card electrical performance with that of the end-use application.

This presentation will cover the key components of the probe card solution that were required, defined, and subsequently developed to achieve the required probe card performance, enabling successful implementation into High-Volume Manufacturing (HVM). We will discuss the technical challenges, simulations, and manufacturing methodologies involved, as well as the strategies applied to achieve a successful transition to HVM.

 

Fine Pitch RF Calibration and Sensitivity to Variation for RF Wafer Probing

Presenter: Daniel Bock
Title: Technical Director, Development Engineering

Date: Tuesday, June 3
Time: 10:30 a.m. – 11:00 a.m.

As RF component performance increases, the pitch of RF devices decreases due to rising frequency requirements and smaller package demands. This trend is driven by factors such as increased 5G content and higher channel counts in high-speed SerDes components.

As a result, probe cards must contact these narrow pitches and enable RF calibration above 67 GHz using compatible calibration substrates. Traditionally, calibration substrates support pitches of 100 µm and above. However, miniaturization is pushing requirements to 80 µm.

To support this, FormFactor is enhancing its manufacturing capabilities to match the reduced pitch. A potential consequence is increased sensitivity to process variations, which may impact calibration accuracy and repeatability. This presentation will present data showing how process biases in calibration standards affect results, including S-parameter measurements and changes in extracted inductance and capacitance. It will illustrate how process variation influences calibration accuracy in wafer testing.

 

Broadband Attenuators Using Thin Film for Wafer Sort

Presenter: Pratik Ghate
Title: Sr. Principal RF Engineer

Date: Tuesday, June 3
Time: 1:30 p.m. – 2:00 p.m.

Receivers for high-speed digital applications like SERDES and PCIe Gen 7 assume signals are highly attenuated due to long transmission paths. However, in wafer sort loopback testing, signal paths are short with minimal attenuation. To emulate real-world test conditions, it’s critical to integrate specific-value attenuators in probe cards to prevent signal clipping and distortion.

Current methods use surface-mount resistor networks (e.g., Pi, H, O, L, and T configurations) or active devices like voltage-controlled attenuators or op-amp-based circuits. These approaches are limited above 50 GHz, constrained by available resistor values and physical size, and affected by parasitics like stray inductance and capacitance.

To address this, we propose a broadband RF attenuation method (≥60 GHz) using thin-film resistor networks. Thin-film designs improve electromagnetic performance, reduce circuit size, and fit within compact probe heads. They also allow for optimized layouts and support attenuation values from >-10 dB to <-20 dB across multiple configurations (Pi, H, O, L, T).

 

Hope to see you in Carlsbad!