Join FormFactor at SWTest 2023 from June 5 – 7 in Carlsbad, CA at the Omni La Costa Resort. We’ll be giving several technical presentations worth attending.

Monday, June 5, 10:30 – 11:00am: On Membrane Attenuators for 60 GHz Loopback Transceiver Testing

Andrew Nelson, RF Application Engineer, FormFactor

Herve Piuzin-Roux, ST Micro

Nicolas Falcot, ST Micro

On-wafer testing of transceivers often requires feedback configurations where the transmitters output is fed back into the receiver. Because of this, there is a need to attenuate the feedback signal to avoid saturation of the receiver. Traditionally, this has been achieved by feeding the signal to a coaxial attenuator and then fed back into the receiver. A new solution has been developed which replaces the coaxial attenuator with on-membrane attenuation structures.

These structures were implemented as RF couplers. The design process had four key requirements; frequency, bandwidth, maximum power, and required coupler attenuation with high reproducibility over test sites and cards, removing the need of de-embedding. The coupler design is compact and can easily integrate onto a membrane between the TX and RX pins of the Device Under Test (DUT). The coupler design was simulated in HFSS and then manufactured on Form Factor’s Pyramid Probe two metal layer membrane technology. The couplers’ final attenuation was measured and compared to simulated results with good correlation between simulation and measurement.

The attenuation over 8 test sites shows an improved standard deviation of 0.35 dB on two membranes, where the previous membrane version showed 1.5 dB. This paper will look at the initial application and its design challenges, an improved design using on membrane attenuator-couplers and the associated performance focusing in on measured vs simulated coupler attenuation and overall improvement of the transceiver test solution performance and robustness.

Monday, June 5, 2:00 – 2:30pm: Fully Automated Integrated Silicon Photonic Wafer Test

Dan Rishavy, Director Product Marketing, FormFactor

Golam Bappi, Senior Photonic Test Engineer, Ayar Labs

Integrated silicon photonics has found extensive use in modern high speed optical links. These optical transceivers are composed of various structures which require extensive passive, DC, RF, and electro-optic characterization at wafer level. A high degree of automation in addition to minimal reconfiguration of the test setup is necessary to improve test throughput. Herein we discuss the use of the CM300 silicon photonics probe station to enable automated full wafer characterization of various passives, DC electro-optic, and VNA measurements of thermal phase shifters, modulators and photodetectors.  FormFactor’s Pharos technology that enables industry proven wafer level automated edge coupling test capability will also be described.

Tuesday, June 6, 8:30 – 9:00am: Pyramid Probe – RF Calibration and Probe Aging Considerations in HVM HighSpeed IO Devices

Daniel Bock, Sr. Staff Applications Engineer, FormFactor

The growth in AI (such as ChatGPT and BING AI) is requiring large investments into the expansion of data centers, driving higher and higher data rates in IO devices.  In order to reach these data rates, wafer test is moving to bandwidth > 60 GHz.  Pyramid Probes are widely used for wafer test at up to 81 GHz and in high volume manufacturing (HVM).  These probes feature micro-strip or CPW transmission lines that provide controlled impedance and low loss (<6 dB at 67 GHz) for the industry leading performance at wafer test.  However, in the standard layout, the signal trace faces the wafer and is only 70 um away, so that it can sometimes couple to structures on the wafer.  This coupling can have significant effects in some cases, in both DUT performance and RF calibration of the probe head.

Further, one expects the coupling to increase as the probe ages and the tips become shorter, bringing the microstrip closer to the wafer.  To reduce this coupling, Pyramid Probes using a microstrip with the ground between the transmission line and the wafer (inverted microstrip) are available.  In this study, we will use probes with standard and inverted microstrips to measure TIA (transimpedance amplifier) performance.  Measurements before and after aging the probes will be compared to characterize these effects.  In addition, we will look at different calibration methods (SOLR, SOLT, SOL de-embed) and compare them to provide recommendations for calibration.

Tuesday, June 6, 10:00 – 10:30am: Maximizing CCC in a Probe Card and the March to an Unburnable Probe

David Raschko, Director Product Marketing, FormFactor

Datacenters and High-Performance-Compute (HPC) applications are quickly approaching and even exceeding 1kW of total power in a single chip in normal operating conditions. In addition to new applications, the transition to new nodes further increases the total power per unit area in a semiconductor, which compounds the challenge of increased power and thermal output of a device during test in even low-power consumption applications such as mobile application processors. This continuous increase in device output power creates several challenges regarding wafer test, particularly with maintaining contactor integrity at high current and in high-temperature environments. To combat this trend, higher CCC in the probe during test must advance in a rate similar to the increased power being observed in the DUT leading to increased uptimes and lower cost of test. This paper will address several techniques that can be utilized in the probe card to maximize CCC to achieve an effective CCC of >2.5A in a probe card at a 80um minimum pitch including both new probe developments along with architectural improvements to maintain probe integrity in a high-stress, high-current environment.

Tuesday, June 6, 1:30 – 2:00pm: Considerations for Vertical High Probe Count Testing

Keith Martin, Sr. Director Product Marketing, FormFactor

As semiconductor suppliers strive to increase their throughput and lower their test costs, probe card parallelism continues to increase.  State of the art probe card designs require up to 80,000 probes and the industry is driving for as much as 150,000 probes in the future.  Where are the limitations?  Total probe force will be >200 kgf and while there are testers that can handle this amount of force, probe card deflection needs to be considered to maintain high volume production requirements.

Today, the ratio of actual overtravel on the probes to the programmed overtravel can be as low as 30% which makes achieving low contact resistance between probe tip and wafer a challenge.  Increasing probe card stiffness is simple in theory but the space constraints between probe card and tester plus the need to populate the PCB with many components makes this very difficult to achieve.  In addition to the tester, the prober and probe card metrology tools will need to accommodate this higher force as well.  This paper will provide a survey of the test equipment industry and identify the chief limitations including where probe card mechanical design needs to improve.

We’ll also be exhibiting in Booth 403 so swing by and say hello! You can find more information at the SWTest 2023 website.