FormFactor is pleased to announce that four papers were accepted for presentation at Test Vision Symposium, July 10-11, at The Moscone Center in San Francisco. Here’s a preview:

Optical Edge Coupling Method for Fully Automated PIC Wafer-Level Testing
Dan Rishavy, Strategic Market Development Director

As the field of silicon photonics grows, there is an increasing need for efficient optical on-wafer testing of photonic integrated circuits (PICs). Traditionally, grating couplers have been used for this purpose, but they come with limitations such as high polarization dependence, limited bandwidth, and low coupling efficiency. Recently, edge couplers have emerged as a favorable alternative for photonic foundries due to their lower polarization dependence, reduced coupling losses, and compatibility with advanced packaging technologies, making them highly suitable for various applications.

Despite these advantages, the adoption of edge couplers for wafer-level testing has been slow compared to grating couplers. This is mainly due to the complexities associated with edge coupling and the high level of skill required for its calibration automation. Although there have been discussions and experiments regarding edge coupling at the wafer level in recent literature, a fully automated solution has yet to be demonstrated.

In this presentation, we will showcase a fully automated turnkey solution developed by FormFactor Inc. We will provide a detailed overview of the system and demonstrate the repeatability of results obtained on a 200 mm photonic wafer. We are introducing an innovative optical probing technique designed for automated on-wafer measurements that leverages edge coupling but can also accommodate surface coupling.

The system is centered around the FormFactor CM300-SiPh probe station equipped with the Pharos Probe. This setup includes a comprehensive, fully automated probe station (FormFactor CM300xi) integrated with an eVue machine vision-based microscope and a 6-axis optical positioner (utilizing PI HexaPod H-811 and NanoCube P-611.3). The optical probe employs a fiber array with optical lenses, details of which will be further discussed in the presentation. The automated algorithm optimally calibrates and maneuvers the optical probe in the Y and Z directions to locate the point of maximum signal intensity, ensuring optimal coupling. This solution addresses a broad spectrum of photonics testing requirements and represents a significant advancement in the field of photonic testing.

Cryogenic Wafer-Scale Characterization of Superconducting Resonators for Improved Fabrication Yield
Brandon Boiko, Cryogenic Applications Engineer

Superconducting resonators play a crucial role in the readout of superconducting transmon qubits. As quantum computers increase in scale, the yield of fabrication emerges as a vital factor for their success. Fabrication errors can lead to greater variability and deviations from the intended design parameters. For superconducting devices, these inaccuracies may cause problems such as frequency crowding and insufficient coupling to the qubit.

To address this, we utilized a 4K wafer prober to compile a statistical dataset on the center frequencies of superconducting readout resonators across an entire wafer. Measurements were taken using a single port probe in a hanger-mode configuration. From these measurements, we generated wafer maps that illustrate the frequency variations, providing valuable insights that can help refine the fabrication process.

Risk Mitigation Strategies for mmWave Production Test Environments
Ryan Garrison, Senior Product Business Manager, Probes Business Unit

With the full deployment of the 5G mobile network, antenna transceivers operating within the 24.25 GHz to 43.5 GHz frequency bands have become essential components in high-end smartphones. These transceivers employ sophisticated beam steering and beamforming techniques to enhance wireless data transmission, requiring precise phase control over up to 32 RF signals. It is critical to verify these chips as Known Good Die before they are integrated into modules, necessitating the use of probe cards and testing equipment that can achieve laboratory-grade precision in RF measurements on a production scale.

The use of membrane-based probe technologies addresses these electrical requirements but introduces higher forces, requiring careful setup and system deflection management to maintain optimal contact performance and durability. This challenge increases when testing is scaled up to improve cost-effectiveness. For example, in an eight-site probe head configuration, the system manages hundreds of nets—nearly a third of which are RF signals—through roughly 5000 probe contacts, generating between 50-80 kg of probing force.

This presentation will explore various strategies and the use of specific equipment to collect empirical data on Actual vs. Programmed Overtravel in multi-site RF probe cards. We will discuss how this data aids in developing baseline models for predictive Finite Element Analysis modeling, which will inform enhancements in future applications. These approaches help address some of the common risks associated with mmWave chip testing in high-volume manufacturing settings, ultimately aiming to lower the overall Cost of Test.

Advanced Probe Card Solutions to Address HBM Wafer and Stacked Die Test Challenges
David Cooke, Senior Product Marketing Manager, Probes Business Unit

Over recent years, Advanced Packaging has undergone substantial developments. High Bandwidth Memory (HBM) has become a primary driver of revenue growth for Memory Manufacturers, thanks to the adoption of 2.5D and 3D packaging technologies. This discussion centers on the challenges Memory Manufacturers encounter when using probe cards to ensure Known Good Die (KGD) testing. With HBM3e, there are millions of bits transferred from GPUs to Memory Stacks at rates of 9.6 GT/s (gigatransfers per second), a process that demands greater power and the capacity to manage the increased heat dissipation brought by each new version of HBM. Additionally, each iteration comes with an increased number of stacked die, which poses challenges in maintaining stable probe to pad alignment due to the heat.

In this session, we will explore the use of thermally scaled MEMs probe card technology for sorting and KGD testing, addressing how it can accommodate the thermal demands of modern memory technologies.