Last week at the SWTest Conference, FormFactor had the privilege of delivering several presentations. Here’s a recap:

Narrow Pitch Impedance Standard Substrates (ISS) for Pyramid Probe Applications – Pratik Ghate, FormFactor

The growth of Large Language Models (LLMs) like ChatGPT, BING AI, and Google BARD/Gemini has led to a rapid increase in demand for faster and more efficient optical communication. To meet this need, operating frequencies and bandwidths must increase, driving demand for more integrated and compact solutions. This manifests in the need for higher data rates in IO devices (such as transimpedance amplifiers (TIAs), laser diodes, etc.) to enable real-time communication, ensure scalability, and improve system efficiency and performance, thereby making higher data rates essential to meeting the evolving demands of applications driven by LLMs.

To ensure high DUT yield, wafer tests at >=60 GHz are essential to validate IO devices capable of achieving these higher data rates. Pyramid Probes provide high-quality device under test (DUT) characterization in wafer tests beyond 67 GHz in high-volume manufacturing (HVM) environments, making them an ideal solution for this need.

As DUT size decreases, pitch follows suit, with a drive to pitches <100 um. These narrow pitches provide various advantages such as a reduction in parasitic capacitance and inductance and enable increased device density necessary for advanced packaging technologies solutions.

In this paper, we discussed the impact of narrower pitches and smaller pad dimensions on DUT characterization in the context of ISSs. We will review the challenges of signal coupling and signal crosstalk that affect signal integrity, and other strategies for reducing calibration standards sizes and their impacts on various calibration methods.

Risk Mitigation Strategies for mmWave Production Test Environments (Best Overall Presentation Award) – Kevin Ayers, Ryan Garrison, FormFactor

With the 5G mobile network in full deployment, antenna transceivers operating in the 24.25 GHz to 43.5 GHz frequency bands have become integral components of high-end smartphones. These transceivers utilize advanced beam steering and beamforming techniques to optimize wireless data transmission, necessitating precise phase control across up to 32 RF signals. Ensuring these chips are verified as Known Good Die prior to module integration is crucial, demanding probe cards and testing equipment that deliver laboratory-grade precision in RF measurements at production scales.

Employing membrane-based probe technologies meets the electrical demands which result in higher forces, necessitating meticulous setup and system deflection management to ensure optimal contact performance and durability. This challenge is further compounded when scaling test parallelism to reduce the Cost of Test. For instance, with an eight-site probe head configuration, there are hundreds of nets, nearly a third of them being RF signals, interacting through approximately 5000 probe contacts, and resulting in 50-80 kg of probing force.

This presentation delved into several strategies and the utilization of specific equipment to gather empirical data on Actual vs. Programmed Overtravel in multi-site RF probe cards. We will explore how this data informs the development of baseline models for predictive Finite Element Analysis modeling, paving the way for enhancements in future applications. These methodologies mitigate some of the prevalent risks associated with mmWave chip testing in high-volume manufacturing contexts, ultimately contributing to a reduction in the overall Cost of Test.

Optical Edge Coupling Method for Fully Automated PIC Wafer-Level Testing – Anna Paczek, IHP Leibniz-Institut f. innovative Mikroelektronik – Germany, Dan Rishavy, FormFactor

As the field of silicon photonics applications expands, so does the demand for high-throughput optical on-wafer testing of photonic integrated circuits (PICs). The well-known grating couplers used for many years for on-wafer testing have many drawbacks such as high polarization dependence, reduced bandwidth, and relatively low coupling efficiency.

Recently, the edge coupler has become a prominent candidate for photonic foundries as a coupling interface to the chip. The low polarization dependence, low coupling loss, and compatibility with advanced packaging solutions make this interface very attractive for many applications. However, testing on the wafer level using edge coupling has lagged behind grating coupler-based probing due to the complexity of the method and problems that need to be overcome. The calibration automation was always complex and heavily dependent on the skills of the operator. In recent years, there have been some concepts and experiments in the literature regarding edge coupling on the wafer level. To date, though, a fully automated solution has not been demonstrated. In this presentation, we would like to demonstrate the fully automated turnkey solution that has been developed by FormFactor Inc. We will provide an overview of the system and show repeatability results obtained on a 200 mm photonic wafer. We propose an alternative optical probing technique suitable for automated on-wafer measurements based on edge coupling, but that can also be used for surface coupling. Here, we evaluate a solution based on FormFactor’s CM300-SiPh probe station and the Pharos Probe. A brief overview of the system is given, and the repeatability of the coupling across the wafer is investigated. The solution is suitable for a wide range of photonics test requirements. The overall system is based on a fully automated Probe Station (FormFactor CM300xi) with an advanced eVue machine vision-based microscope system and 6-axis optical positioner (based on PI HexaPod H-811 and NanoCube P-611.3). The optical probe is a fiber array with optical lenses and will be described further in the presentation. The automated algorithm calibrates and moves the optical probe in Y and Z directions to find the maximum signal intensity and thus the best coupling point.

Advanced Probe Card Solutions to Address HBM Wafer and Stacked Die Test Challenges – David Cooke, Kalyanjit Ghosh, FormFactor

Advanced Packaging has evolved significantly over the last few years. High Bandwidth Memory has emerged as the leading revenue growth opportunity for Memory Manufacturers, with 2.5D and 3D package technologies. This discussion is focused on problems Memory Manufacturers face when utilizing probe cards to ensure Known Good Die (KGD) test. Millions of bits are exchanged from GPU to Memory Stacks (9.6 GT/s (gigatransfers per second)) with HBM3e. This dynamic is demanding more power and the ability to handle heat dissipated by each new HBM version, each with an increased number of stacked die which in turn will result in problems for the probe card to withstand this heating and provide stable probe-to-pad alignment. In order to respond to these challenges, we will discuss thermally scaled MEMS technology for sorting and KGD.