COMPASS – Tokyo is happening on February 28, 2023 in Tokyo, Japan. The user conference will have a number of presentations from FormFactor and partners. Here’s a quick rundown:

Quantum/CryoCMOS: Enabling the Future of Computing

Dong-Thuc Knobbe

Quantum computing development is accelerating and showing promise to commercialize in the next years however key challenges must be addressed in the fabrication and test of superconducting devices used for this purpose.

Superconducting or spin qubit devices go through complicated fabrication processes involving multiple additive and subtractive steps. As well, prior to characterization, time consuming and expensive techniques such as wire bonding and packaging are required.

Low performance devices and defective qubits lead to wasted time and money on unnecessary equipment cooldowns on deployment systems and slow down critical feedback for new fabrication processes. Pre-characterization measurements on quantum processors can establish resonator quality and qubit yield prior to the dilution refrigerator cooldown that can prevent this wasted time and money on cooling down poor devices.

The test and measurement temperature is typically close to absolute zero, in the range of 4 K to sub-50 mK, for quantum qubit device characterization.

This presentation will discuss these challenges and present use-cases from mK up to 77 K chip scale probing as well as wafer scale probing; all of which can incorporate FormFactor’s probe interface technology.

FRT Metrology for Advanced Packaging

Chikashi Ito

In Advanced Packaging new technologies were developed to achieve devices with high density in a small space, ultimately leading to “hybrid bonding” with even the highest density so far, which enables a higher bandwidth and an increased power. Currently, micro bumps and hybrid bonding are coexistent, as hybrid bonding is not required in all areas. In this regard, the need for flexibility in wafer metrology has just exploded in the past, and with new technologies and processes, it seems to keep growing even further and even faster.

FRT’s MicroProf® AP tool is specifically designed for metrology of Advanced Packaging applications. The tool measures and handles numerous wafer types up to 12” for front- and back-end, at different 3D packaging process steps, as well as glass, lens and non-SEMI standard wafers, wafers on tape in frame. With our SurfaceSens™ multi-sensor technology, the modular based software and retrofittable sensor hardware, we create the flexibility that customers need in heterogeneous production cycles.

  • FRT Metrology solutions in Advanced Packaging
  • High-precision micron-level process control of RDLs
  • CMP die and wafer flatness evaluation for planarization and hybrid bonding


Fire Probe Card: Double-Side Probing Solution

Yoichi Funatoko

We will introduce the evaluation results of the Fire Probe Card developed for the Cascade double-sided prober PA200DSP.

The probe test is performed from the bottom side of the wafer, and the temperature of the wafer is controlled by the heater on the probe card PCB.

We plan to present wafer temperature measurement data, prober chuck and probe card thermal Z expansion position, and 20 nano seconds pulse width voltage measurement results at 85°C.


Silicon Photonics: Challenges and Opportunities for Wafer-Level Photonics Test

Dan Rishavy

The integration of optical components on a chip creates a host of new challenges and demands for wafer-level probing of photonics devices, where huge volumes of device-performance data are required to carry a design from concept to qualification and into production. While working in a lab on an initial prototype, it may suffice to spend minutes or in some cases hours to setup and align a single device for measurements. However, such time- and effort-intensive methods are unsuitable for the cycle-time demands of volume SiPh manufacturing. Due to the industry demand for a wide range of applications, a flexible probing platform is needed that can be quickly optimized for the needs of the application. Numerous parameters can be configured on FormFactor’s wafer probers to enable optical, RF, DC, wafer level, die level, surface coupling, edge coupling, and probe cards.  While maintaining the required alignment performance requirements in terms of accuracy, throughput, and power coupling repeatability.  Come to this session to learn more about FormFactor’s exciting technology enabling the Silicon Photonics market expansion.


Single Sweep Broadband S-Parameter Measurements to mm-wave for Semiconductor Transistor and IC Test to 220 GHz

Toru Sugawara

Measurements beyond conventional coaxial limits often means more frequent changes to the banded setup. For some time there have been requests to enable measurements to go all the way to 220 GHz in a single sweep with performance levels equivalent to conventional coaxial approaches. In this presentation we will show the new optimized single sweep solution with some initial measurements. We will also present typical analytical approaches to evaluate the performance of the system using python and WinCal. We will also show the new storage pod design to enable quick and safe band swaps if needed beyond 220 GHz.


Known Good Die Memory Wafer Test Challenge Beyond DDR5 4 GHz/8 Gbps Speed

Alan Liao

With the recent demand for advanced packages, demand for wafer-level high-speed testing of DRAM and NAND FLASH is rapidly growing. This presentation will introduce FFI’s approach to the speed, temperature, and efficiency required for KGD, based on the trends in advanced packages.


For more information visit COMPASS 2022 – Tokyo, Japan.