2D MEMS Probe to Parametric Testing and Other Probe Technology | Saeki
Best Overall Presentation - SWTEST Asia 2019
In his paper, FormFactor’s Takao Saeki unveils Takumi CL, a new low-impact parametric MEMS probe card for low-leakage and small pad size applications. Featuring a new 2D MEMS spring and contact tip, the Takumi CL offers a consistent small scrub mark over the life of the product, with the benefits of low cost and fast manufacturing lead time.
Ultra High Temperature Probe Card Solution for Automotive IC Testing | Liao
In this paper, we will discuss overall industry trend of automotive IC growth and technology trends, wafer test challenges and FromFactor’s solution to enable massive parallel testing of >=128 DUT parallel test on automotive micro-controller device, from -40C to 160C. We will also share extensive engineering characterization results on prober deflection and thermal behavior, high pin count probe card AOT vs. POT, low force MEMS probe on wafer pad to achieve zero defect IC wafer probing requirements.
Improving Wafer-Level S-parameters Measurement Accuracy and Stability with Probe-Tip Power Calibration up to 110 GHz for 5G Applications | Sia
This paper presents a novel method of probe-tip power calibration for S-parameters calibration which is shown to greatly improve DC biasing accuracy, S-parameters measurement accuracy and post-calibration stability up to 110 GHz.
Advanced Packaging, Heterogeneous Integration and Test | Slessor
Major products rely on advanced packaging to reach the market; a groundswell of die-integration technologies are revolutionizing packaging, assembly, and test.
Advanced Packaging - It's Changing the World of Wafer Test | Slessor
Presented at TestVision - Semicon West 2019
Automotive IC Production Wafer Test In a Zero-Defect World | Leong
Chip Scale Review asked FormFactor CMO, Amy Leong to respond to questions that provide insights into challenges associated with automotive IC production wafer testing amid the requirement for zero-defects.
Silicon Photonics: Automated wafer-level probing meets silicon photonics | Frankel, Negishi, Simmons, Rishavy, Christenson
As chip designers are pressed for ever-increasing data rates, the use of wavelength-division multiplexing (WDM) with infrared photonic signals as a data transfer medium is increasingly finding its way into CMOS silicon-based devices. Termed “silicon photonics” (SiPh), this technology is not only being used to displace traditional electrical interconnects, but also for a broad range of applications, including lidar, quantum computing, and biosensing.
Companies developing 5G technologies are racing to develop the first chipsets in order to set the standard of deployment and be the leader. While initial standards for 5G were set at the end of 2017, and there are ideas about the applications of 5G, it is still unclear how exactly it will all come together. This article explores the challenges and changes in test methodology of 5G devices, and showcases the results of a collaboration with Intel.
5G Wafer Test and the New Age of Parallelism | Bock, Sia
Best Overall Presentation - SWTEST 2019
The development of new RF devices (5G and high speed digital components) is changing the landscape for RF probing. For many years, RF probing in frequencies beyond cell phone and WiFi frequencies was a niche area, only requiring a very small number of lines as well as not meeting the needs for High Volume Manufacturing (HVM).
Silicon Photonics Challenges and Solutions for Wafer Level Production Tests | FormFactor & Global Foundries
Most Inspirational Presentation - SWTEST 2019
Data centers around the world currently consume about 7% of the earth’s total power output. To satisfy the increasing demands for cloud computing and support emerging applications such as artificial intelligence, genomics revolution and data analytics, hyperscale data centers are being built around the world at an accelerated pace, with analysts predicting up to 20% of earth's total power output consumed by data centers in 2030
High Density Probe Card PCBs - Are You Your Own Worst Enemy to Achieving Higher Parallelism on your Designs? | Powell, Ojeda
Best Presentation Tutorial in Nature - SWTEST 2019
As Probe Card PCB’s complexity, and net counts increase most customers are not paying enough attention to their Power/Channel assignments to make their High Density PCB Designs possible to manufacture. Compounding this issue are tester manufacturers that create Non-optimal Channel assignment restrictions on their testers. This further complicates your ability to achieve higher parallelism testing.
Hybrid MEMS Technology 2.0 | Kister, Leong, Bhardwaj
At 2017 SWTest workshop, Qualcomm and FormFactor introduced the innovative Hybrid MEMS probe technology for advanced probing application. Hybrid MEMS technology allows multiple probe designs to be used in a single probe head design, with each probe design optimized for a specific purpose. The technical innovation to enable Hybrid design is to leverage multi-layer composite MEMS fabrication technology, which allows the optimal wafer test performance by including otherwise mutually exclusive requirements such as fine-pitch and high current carrying capability.
Improving Signal Fidelity in High Parallelism Probe Card via TTRE | Young-woo, Quay
With DRAM process node transitioning to 1X, 1Y, and 1Z, die shrinkage is driving die per wafer to the level of 2000 device or more. Wafer test using a single touchdown probe card is inevitable and can be achieved using tester resource enhancement without having to spend an excessive amount of capital expenses to upgrade existing ATEs.
Probing 5G Devices Like Its No Big Deal | Lesher, Rhodes
The rollout of 5G networks is in its infancy, but the demand for 5G devices is already here. Those devices will be in consumer products like phones, but they’ll also be integrated into new infrastructure all around us – and volumes will be hefty as a result. As with any high volume ICs, comprehensive, multi-site testing at the wafer level offers the lowest cost of test, but 5G devices have challenges not seen before in volume production. The need to support many tens of signals in the many tens of GHz range is in fact a big deal.
A Fully Automatic Electro Optical Test System Enabling the Development of a Silicon Photonics Technology Platform | FormFactor & imec
A fully automatic system for wafer-level testing of photonic devices is presented. The test system is deployed for optical process control monitor (PCM) characterization to support the ongoing development of a silicon photonics technology platform.
5G: The Next Disruptive Technology in Production Test | Bock, Bishop, Damm
Break the Myth of Wafer Probing On Cu for Fan-out Wafer Level Packaging (FOWLP) | Bhardwaj, Leong, Kim, Hyun
LED Wafer Test - SWTest Asia | Funatoko
Verification of Singulated HBM2 stacks with Die Level Handler | Armstrong, Kiyokawa, Nhin
High Parallelism Probe Card on V93000 Direct-Probe™ System to Increase Testing Throughput on Automotive ICs | Heitzer, Chen, Effenberg, Hirschmann, Zuendorf, Liao, Phipps
Advanced Testing Technology for Emerging Automotive Applications | Stillman, Leong, Bhardwaj
Verification of HBM through Direct Probing on MicroBumps | Loranger, Moon
High performance HBM Known Good Stack Testing | Loranger, Oonk
Determining Probe’s Maximum Allowable Current | Cassier, Folwarski, Kister, Leong
Winner of “Most Inspirational Presentation”
Minimizing Parametric Probe Card Stray Capacitance | Soler, Levy
Reliable Testing of Cu Pillar Technology For Smart Devices | Bezuk, Cassier, Leong, Miller, Slessor, Syed, Zhao
Cost Effective 1,000V High Voltage Parametric Test Technique | Andoh, Ishibiki, Kawamata, Funatoko
Advance Low Force Probe cards Used on Solder Flip Chip Devices | Stillman, Hughes
Key Considerations to Probe Cu Pillars in High Volume Production | Wittig, Leong, Nguyen, Masi, Kister, Slessor
Winner of “Best Overall Presentation”
Can Testers and Probe Cards Keep Up With Speed Requirements for Image Sensors? | Levy, Kawamata, Hamajima
International Technology Roadmap for Semiconductors | Armstrong, Feldman, Loranger
Probing Study of Fine-pitch Cu Pillars | Leong, Wittig, Nguyen, Hulic, Slessor
Trends, Challenges, and Solutions in Advanced SoC Wafer Probe | Slessor, Kister, Eldridge, Nguyen, Leong
When Brick Wall is Not the Best, PART II (A Touch Down Optimization Study) | Wegleitner, Berry
IEEE Semiconductor Wafer Test Workshop, 28nm Mobile SoC Copper Pillar Probing Study | Horas, Leong, Hulic
28nm Mobile SoC Copper Pillar Probing Study | Horas, Leong, Hulic
Actual vs. Programmed Over Travel for Advanced Probe Cards | Berry, Breinlinger, Rincon
IEEE Semiconductor Wafer Test Workshop, Key Design Parameters to Maximize Probe Current Carrying Capability | Kister
Winner of "Best Paper-Tutorial in Nature"
High Speed Control Bus for Advanced TRE™ | Huebner
Winner - Best Presentation, Tutorial in Nature
MicroProbe Vx-RF Probe Card Technology | Slessor, Kister, Degan, Nagler, Nouri
IEEE Semiconductor Wafer Test Workshop, MicroProbe Vx-RF Probe Card Technology | Nagler, Degen, Nouri, Kister & Slessor
MicroProbe Vx-MP Probe Card Technology | Kister, Hopkins
Electrical Contact Resistance - The Key Parameter in Probe Card Performance | Kister, Hopkins
Winner - Best Data Presentation
Wafer Probing Scrub Analysis to Optimize KGD Applications | Wang, Martens, Wijeyesekera, Matsubayashi, Napier, Leong
Key Methods in Reducing Pad Crack Risk at Probing Low-k Wafers | Romreill, Leong
Probes A New Dimension in Probe Count | Huebner, Hatsumori, Pritzkau, Kawamata, Matsuo
Cost-Effective Fully Tested Die with High Frequency and High Throughput Wafer Test Solution | Ozawa, Minamihashimoto, Sagamihara